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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f32219b224sm10630335ad.294.2024.05.22.04.27.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 May 2024 04:27:12 -0700 (PDT) Message-ID: Date: Wed, 22 May 2024 08:27:08 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] target/riscv: Move Guest irqs out of the core local irqs range. To: Rajnesh Kanwal , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com References: <20240520125157.311503-1-rkanwal@rivosinc.com> <20240520125157.311503-3-rkanwal@rivosinc.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20240520125157.311503-3-rkanwal@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 5/20/24 09:51, Rajnesh Kanwal wrote: > Qemu maps IRQs 0:15 for core interrupts and 16 onward for > guest interrupts which are later translated to hgiep in > `riscv_cpu_set_irq()` function. > > With virtual IRQ support added, software now can fully > use the whole local interrupt range without any actual > hardware attached. > > This change moves the guest interrupt range after the > core local interrupt range to avoid clash. > > Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") > Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") > > Signed-off-by: Rajnesh Kanwal > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/cpu_bits.h | 3 ++- > target/riscv/csr.c | 9 ++++++++- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 74318a925c..a470fda9be 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -695,7 +695,8 @@ typedef enum RISCVException { > #define IRQ_M_EXT 11 > #define IRQ_S_GEXT 12 > #define IRQ_PMU_OVF 13 > -#define IRQ_LOCAL_MAX 16 > +#define IRQ_LOCAL_MAX 64 > +/* -1 is due to bit zero of hgeip and hgeie being ROZ. */ > #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) > > /* mip masks */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 152796ebc0..464e0e57a3 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1148,7 +1148,14 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, > > #define VSTOPI_NUM_SRCS 5 > > -#define LOCAL_INTERRUPTS (~0x1FFF) > +/* > + * All core local interrupts except the fixed ones 0:12. This macro is for > + * virtual interrupts logic so please don't change this to avoid messing up > + * the whole support, For reference see AIA spec: `5.3 Interrupt filtering and > + * virtual interrupts for supervisor level` and `6.3.2 Virtual interrupts for > + * VS level`. > + */ > +#define LOCAL_INTERRUPTS (~0x1FFFULL) > > static const uint64_t delegable_ints = > S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;