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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4548e6a5b65sm31614561f8f.8.2026.05.11.23.38.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 May 2026 23:39:00 -0700 (PDT) Message-ID: Date: Tue, 12 May 2026 08:38:58 +0200 Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: eric.auger@redhat.com Subject: Re: [PATCH v4 03/17] target/arm/cpu-sysregs.h.inc: Update with automatic generation To: Shameer Kolothum Thodi , "eric.auger.pro@gmail.com" , "qemu-devel@nongnu.org" , "qemu-arm@nongnu.org" , "kvmarm@lists.linux.dev" , "peter.maydell@linaro.org" , "richard.henderson@linaro.org" , "cohuck@redhat.com" , "sebott@redhat.com" , "philmd@linaro.org" Cc: "maz@kernel.org" , "oliver.upton@linux.dev" , "pbonzini@redhat.com" , "armbru@redhat.com" , "berrange@redhat.com" , "abologna@redhat.com" , "jdenemar@redhat.com" References: <20260503073541.790215-1-eric.auger@redhat.com> <20260503073541.790215-4-eric.auger@redhat.com> From: Eric Auger In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: 5L4RgsKQX00GJc0MEUl6RxLNx1nkx4yf5SsnQ769Fus_1778567941 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Shameer, On 5/7/26 10:45 AM, Shameer Kolothum Thodi wrote: > >> -----Original Message----- >> From: Eric Auger >> Sent: 03 May 2026 08:33 >> To: eric.auger.pro@gmail.com; eric.auger@redhat.com; qemu- >> devel@nongnu.org; qemu-arm@nongnu.org; kvmarm@lists.linux.dev; >> peter.maydell@linaro.org; richard.henderson@linaro.org; >> cohuck@redhat.com; sebott@redhat.com; Shameer Kolothum Thodi >> ; philmd@linaro.org >> Cc: maz@kernel.org; oliver.upton@linux.dev; pbonzini@redhat.com; >> armbru@redhat.com; berrange@redhat.com; abologna@redhat.com; >> jdenemar@redhat.com >> Subject: [PATCH v4 03/17] target/arm/cpu-sysregs.h.inc: Update with >> automatic generation >> >> External email: Use caution opening links or attachments >> >> >> Generated definitions with scripts/update-aarch64-cpu-sysregs-header.py >> based on "AARCHMRS containing the JSON files for Arm A-profile >> architecture (2026-03)" Registers.json file. >> >> Signed-off-by: Eric Auger >> Signed-off-by: Cornelia Huck >> Message-ID: <20251208163751.611186-4-eric.auger@redhat.com> >> --- >> target/arm/cpu-sysregs.h.inc | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc >> index d61f0d0a19..2188cd7be0 100644 >> --- a/target/arm/cpu-sysregs.h.inc >> +++ b/target/arm/cpu-sysregs.h.inc >> @@ -1,15 +1,25 @@ >> /* SPDX-License-Identifier: GPL-2.0-or-later */ >> + >> +/* This file is autogenerated by scripts/update-aarch64-cpu-sysregs- >> header.py */ >> +/* DEF(, , , , , ) */ >> + >> +DEF(AIDR_EL1, 3, 1, 0, 0, 7) >> +DEF(CCSIDR2_EL1, 3, 1, 0, 0, 2) >> DEF(CCSIDR_EL1, 3, 1, 0, 0, 0) >> DEF(CLIDR_EL1, 3, 1, 0, 0, 1) >> DEF(CTR_EL0, 3, 3, 0, 0, 1) >> DEF(DCZID_EL0, 3, 3, 0, 0, 7) >> +DEF(GMID_EL1, 3, 1, 0, 0, 4) >> DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) >> DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) >> DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) >> DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) >> +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2) >> +DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) >> DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) >> DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) >> DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) >> +DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3) >> DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) >> DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) >> DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) >> @@ -39,6 +49,10 @@ DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) >> DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) >> DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) >> DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) >> +DEF(MIDR_EL1, 3, 0, 0, 0, 0) >> +DEF(MPIDR_EL1, 3, 0, 0, 0, 5) > Do we need MPIDR_EL1 as well? Is this considered as a feature ID > register and is writable? I don't think so. MPIDR_EL1 is part of the ID regs range defined in the kernel doc op0 = 3, op1 = {0,1,3}, crn = 0, crm within [0, 7], op2 within [0, 7] That's why the python script extracts it. Effectively it is not writable yet. I can exclude it from the automatic generation but do we really need to? Any specific reason? Thanks Eric > Thanks, > Shameer > >> DEF(MVFR0_EL1, 3, 0, 0, 3, 0) >> DEF(MVFR1_EL1, 3, 0, 0, 3, 1) >> DEF(MVFR2_EL1, 3, 0, 0, 3, 2) >> +DEF(REVIDR_EL1, 3, 0, 0, 0, 6) >> +DEF(SMIDR_EL1, 3, 1, 0, 0, 6) >> -- >> 2.53.0