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intel-xe@lists.freedesktop.org >> Cc: Manna, Animesh ; Shankar, Uma >> >> Subject: [PATCH v4 12/13] drm/i915/display: Add helper to enable DC >> counter >> >> Add xe3lpd_enable_dc_count() to enable the DC_COUNT_EN register. >> Also define DC_STATE_DC3CO_RESIDENCY to read DC3CO residency. >> Needed to retrieve DC residency for DC3CO. >> >> Signed-off-by: Dibin Moolakadan Subrahmanian >> >> Reviewed-by: Uma Shankar >> --- >> drivers/gpu/drm/i915/display/intel_display_power_well.c | 5 +++++ >> drivers/gpu/drm/i915/display/intel_display_power_well.h | 1 + >> drivers/gpu/drm/i915/display/intel_display_regs.h | 5 +++++ >> drivers/gpu/drm/i915/display/intel_dmc.c | 3 +++ >> 4 files changed, 14 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c >> b/drivers/gpu/drm/i915/display/intel_display_power_well.c >> index 3ea080d0e21e..0e7e6a2b1547 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c >> @@ -866,6 +866,11 @@ void gen9_set_dc_state(struct intel_display *display, >> u32 state) >> power_domains->dc_state = val & mask; >> } >> >> +void xe3lpd_enable_dc_count(struct intel_display *display) { >> + intel_de_write(display, DC_COUNT_EN, >> DC_COUNT_EN_COUNTER_ENABLE); } >> + >> static void xe3lpd_enable_dc3co(struct intel_display *display) { >> drm_dbg_kms(display->drm, "Enabling DC3CO\n"); diff --git >> a/drivers/gpu/drm/i915/display/intel_display_power_well.h >> b/drivers/gpu/drm/i915/display/intel_display_power_well.h >> index 8f5524da2d06..0ce64b894436 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h >> @@ -159,6 +159,7 @@ void gen9_set_dc_state(struct intel_display *display, >> u32 state); void gen9_disable_dc_states(struct intel_display *display); void >> bxt_enable_dc9(struct intel_display *display); void bxt_disable_dc9(struct >> intel_display *display); >> +void xe3lpd_enable_dc_count(struct intel_display *display); >> >> extern const struct i915_power_well_ops i9xx_always_on_power_well_ops; >> extern const struct i915_power_well_ops chv_pipe_power_well_ops; diff -- >> git a/drivers/gpu/drm/i915/display/intel_display_regs.h >> b/drivers/gpu/drm/i915/display/intel_display_regs.h >> index efd1a3e56f76..875cd06f2566 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h >> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h >> @@ -3084,6 +3084,11 @@ enum skl_power_gate { >> #define DC_STATE_DEBUG_MASK_CORES (1 << 0) >> #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) >> >> +#define DC_COUNT_EN _MMIO(0x457B4) >> +#define DC_COUNT_EN_COUNTER_ENABLE REG_BIT(31) >> + >> +#define DC_STATE_DC3CO_RESIDENCY _MMIO(0x457B8) >> + >> #define D_COMP_BDW _MMIO(0x138144) >> >> /* Pipe WM_LINETIME - watermark line time */ diff --git >> a/drivers/gpu/drm/i915/display/intel_dmc.c >> b/drivers/gpu/drm/i915/display/intel_dmc.c >> index 4785001644f5..a133785c815b 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c >> @@ -941,6 +941,9 @@ void intel_dmc_load_program(struct intel_display >> *display) >> >> gen9_set_dc_state_debugmask(display); >> >> + if (DISPLAY_VER(display) >= 35) > HAS_DC3CO() check instead of display ver? The check is intentional.DC count is not tied only to DC3CO support, so I used the display version check here. > > Regards, > Animesh >> + xe3lpd_enable_dc_count(display); >> + >> pipedmc_clock_gating_wa(display, false); } >> >> -- >> 2.43.0