Re: [PATCH v4 7/7] drm/i915/dp: Don't limit the Link M/N ratio with the symbol timing generator

["Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>]

On 11/4/2026 7:00 AM, Kandpal, Suraj wrote:
>> Subject: [PATCH v4 7/7] drm/i915/dp: Don't limit the Link M/N ratio with the
>> symbol timing generator
>>
>> The limit on the Link M/N ratio only applies to the pixel based timing
>> generator, there is no such restriction when the symbol based timing
>> generator is used.
>>
>> Bspec: 68922
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c     | 17 +++++++++++++----
>>   drivers/gpu/drm/i915/display/intel_dp_mst.c |  4 +++-
>>   2 files changed, 16 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index
>> 788c16df9801131294c73420c2c0d4d3ec848310..a8fa0809079e8b3f6fb574cfb
>> 73fb6bb8b019cc3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1277,8 +1277,12 @@ static bool intel_dp_has_symbol_tg(struct
>> intel_display *display, bool is_mst, b  }
>>
>>   static int
>> -intel_dp_get_max_m_n_ratio(struct intel_display *display)
>> +intel_dp_get_max_m_n_ratio(struct intel_display *display, bool is_mst,
>> +int link_rate)
>>   {
>> +	/* No Link M/N ratio limit with the symbol based timing generator */
>> +	if (intel_dp_has_symbol_tg(display, is_mst,
>> drm_dp_is_uhbr_rate(link_rate)))
>> +		return INT_MAX;
>> +

This relies on the symbol TG always being used whenever
intel_dp_has_symbol_tg() is true. Unless the suggestions made on patch
5 to incorporate the symbol TG in the link computation path are
adopted, the pixel TG could end up being used without the Link M/N
ratio check.

>>   	if (DISPLAY_VER(display) >= 35)
>>   		return 22;
>>
>> @@ -1308,7 +1312,9 @@ bool intel_dp_can_support_m_n(struct
>> intel_display *display,
>>   			      const struct intel_crtc_state *crtc_state,
>>   			      int pixel_clock, int link_rate)  {
>> -	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
>> +	bool is_mst = crtc_state &&
>> +		      intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
>> +	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display, is_mst,
>> +link_rate);
>>   	enum transcoder cpu_transcoder = TRANSCODER_A;
>>   	u32 link_m, link_n;
>>   	int m_n_ratio;
>> @@ -1331,7 +1337,10 @@ void intel_dp_check_m_n_ratio(const struct
>> intel_crtc_state *crtc_state,
>>   			      struct intel_link_m_n *m_n)
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>> -	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
>> +	int max_m_n_ratio =
>> +		intel_dp_get_max_m_n_ratio(display,
>> +					   intel_crtc_has_type(crtc_state,
>> INTEL_OUTPUT_DP_MST),
>> +					   crtc_state->port_clock);
>>   	int m_n_ratio;
>>
>>   	m_n->bypass_m_n_ratio_limit = false;
>> @@ -2815,7 +2824,7 @@ intel_dp_compute_m_n_ratio_limits(struct
>> intel_dp *intel_dp,
>>   		drm_dbg_kms(display->drm,
>>   			    "[CONNECTOR:%d:%s] No link config with a Link
>> M/N ratio <= %d\n",
>>   			    connector->base.base.id, connector->base.name,
>> -			    intel_dp_get_max_m_n_ratio(display));
>> +			    intel_dp_get_max_m_n_ratio(display, false, 0));
> 
> Just use crtc_state->port_clock instead of 0.
> 
> With that fixed LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> 
>>
>>   		return false;
>>   	}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index
>> 81ac454603603df42db477ddb26cfb2f620dcfea..fe9cdf771f481fc8a8b8f3f29e4
>> a24aa53a53f94 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -1570,7 +1570,9 @@ mst_connector_mode_valid_ctx(struct
>> drm_connector *_connector,
>>   					   min_link_bpp_x16,
>>   					   bw_overhead_flags);
>>
>> -	if (!intel_dp_can_support_m_n(display, NULL, mode->clock,
>> max_link_clock)) {
>> +	/* MST always uses the symbol based timing generator, which has no
>> Link M/N ratio limit */
>> +	if (!HAS_DP_SYMBOL_TG(display) &&
>> +	    !intel_dp_can_support_m_n(display, NULL, mode->clock,
>> +max_link_clock)) {
>>   		*status = MODE_CLOCK_HIGH;
>>   		return 0;
>>   	}
>>
>> --
>> 2.25.1
>