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From: Alejandro Lucero Palau <alucerop@amd.com>
To: Dave Jiang <dave.jiang@intel.com>,
	alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org,
	netdev@vger.kernel.org, dan.j.williams@intel.com,
	martin.habets@xilinx.com, edward.cree@amd.com,
	davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
	edumazet@google.com
Subject: Re: [PATCH v3 09/20] cxl: support type2 memdev creation
Date: Mon, 16 Sep 2024 13:38:32 +0100	[thread overview]
Message-ID: <c874a279-c673-e789-bbf2-6fa68deb9537@amd.com> (raw)
In-Reply-To: <740c2831-4131-4471-b0ae-23eb816e0600@intel.com>


On 9/12/24 19:19, Dave Jiang wrote:
>
> On 9/7/24 1:18 AM, alejandro.lucero-palau@amd.com wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Add memdev creation from sfc driver.
>>
>> Current cxl core is relying on a CXL_DEVTYPE_CLASSMEM type device when
>> creating a memdev leading to problems when obtaining cxl_memdev_state
>> references from a CXL_DEVTYPE_DEVMEM type. This last device type is
>> managed by a specific vendor driver and does not need same sysfs files
>> since not userspace intervention is expected. This patch checks for the
>> right device type in those functions using cxl_memdev_state.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> ---
>>   drivers/cxl/core/cdat.c            |  3 +++
>>   drivers/cxl/core/memdev.c          |  9 +++++++++
>>   drivers/cxl/mem.c                  | 17 +++++++++++------
>>   drivers/net/ethernet/sfc/efx_cxl.c |  7 +++++++
>>   include/linux/cxl/cxl.h            |  2 ++
>>   5 files changed, 32 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
>> index bb83867d9fec..0d4679c137d4 100644
>> --- a/drivers/cxl/core/cdat.c
>> +++ b/drivers/cxl/core/cdat.c
>> @@ -558,6 +558,9 @@ void cxl_region_perf_data_calculate(struct cxl_region *cxlr,
>>   	};
>>   	struct cxl_dpa_perf *perf;
>>   
>> +	if (!mds)
>> +		return;
>> +
>>   	switch (cxlr->mode) {
>>   	case CXL_DECODER_RAM:
>>   		perf = &mds->ram_perf;
>> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
>> index 836faf09b328..5f8418620b70 100644
>> --- a/drivers/cxl/core/memdev.c
>> +++ b/drivers/cxl/core/memdev.c
>> @@ -468,6 +468,9 @@ static umode_t cxl_ram_visible(struct kobject *kobj, struct attribute *a, int n)
>>   	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>>   	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
>>   
>> +	if (!mds)
>> +		return 0;
> I think instead of altering the sysfs visible attributes, what you really want is to not register the unwanted group attributes. Or basically only register the cxl_memdev_attribute_group and not the other ones. Otherwise it gets really messy. And whomever adds future attributes need to also remember the special case. I think you can refer to core/port.c and look at the different decoder types as inspiration for creating different memdev types where it has cxl_decoder_base_attribute_group and then tack on specific attribute groups.
>
> DJ


I think you are right. It was a quick fix for having things working and 
not thought about it in detail.

I'll do and fix it for v4.

Thanks!


>> +
>>   	if (a == &dev_attr_ram_qos_class.attr)
>>   		if (mds->ram_perf.qos_class == CXL_QOS_CLASS_INVALID)
>>   			return 0;
>> @@ -487,6 +490,9 @@ static umode_t cxl_pmem_visible(struct kobject *kobj, struct attribute *a, int n
>>   	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>>   	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
>>   
>> +	if (!mds)
>> +		return 0;
>> +
>>   	if (a == &dev_attr_pmem_qos_class.attr)
>>   		if (mds->pmem_perf.qos_class == CXL_QOS_CLASS_INVALID)
>>   			return 0;
>> @@ -507,6 +513,9 @@ static umode_t cxl_memdev_security_visible(struct kobject *kobj,
>>   	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>>   	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
>>   
>> +	if (!mds)
>> +		return 0;
>> +
>>   	if (a == &dev_attr_security_sanitize.attr &&
>>   	    !test_bit(CXL_SEC_ENABLED_SANITIZE, mds->security.enabled_cmds))
>>   		return 0;
>> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
>> index 7de232eaeb17..5c7ad230bccb 100644
>> --- a/drivers/cxl/mem.c
>> +++ b/drivers/cxl/mem.c
>> @@ -131,12 +131,14 @@ static int cxl_mem_probe(struct device *dev)
>>   	dentry = cxl_debugfs_create_dir(dev_name(dev));
>>   	debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show);
>>   
>> -	if (test_bit(CXL_POISON_ENABLED_INJECT, mds->poison.enabled_cmds))
>> -		debugfs_create_file("inject_poison", 0200, dentry, cxlmd,
>> -				    &cxl_poison_inject_fops);
>> -	if (test_bit(CXL_POISON_ENABLED_CLEAR, mds->poison.enabled_cmds))
>> -		debugfs_create_file("clear_poison", 0200, dentry, cxlmd,
>> -				    &cxl_poison_clear_fops);
>> +	if (mds) {
>> +		if (test_bit(CXL_POISON_ENABLED_INJECT, mds->poison.enabled_cmds))
>> +			debugfs_create_file("inject_poison", 0200, dentry, cxlmd,
>> +					    &cxl_poison_inject_fops);
>> +		if (test_bit(CXL_POISON_ENABLED_CLEAR, mds->poison.enabled_cmds))
>> +			debugfs_create_file("clear_poison", 0200, dentry, cxlmd,
>> +					    &cxl_poison_clear_fops);
>> +	}
>>   
>>   	rc = devm_add_action_or_reset(dev, remove_debugfs, dentry);
>>   	if (rc)
>> @@ -222,6 +224,9 @@ static umode_t cxl_mem_visible(struct kobject *kobj, struct attribute *a, int n)
>>   	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>>   	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
>>   
>> +	if (!mds)
>> +		return 0;
>> +
>>   	if (a == &dev_attr_trigger_poison_list.attr)
>>   		if (!test_bit(CXL_POISON_ENABLED_LIST,
>>   			      mds->poison.enabled_cmds))
>> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
>> index 14fab41fe10a..899bc823a212 100644
>> --- a/drivers/net/ethernet/sfc/efx_cxl.c
>> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
>> @@ -83,6 +83,13 @@ int efx_cxl_init(struct efx_nic *efx)
>>   	 */
>>   	cxl_set_media_ready(cxl->cxlds);
>>   
>> +	cxl->cxlmd = devm_cxl_add_memdev(&pci_dev->dev, cxl->cxlds);
>> +	if (IS_ERR(cxl->cxlmd)) {
>> +		pci_err(pci_dev, "CXL accel memdev creation failed");
>> +		rc = PTR_ERR(cxl->cxlmd);
>> +		goto err;
>> +	}
>> +
>>   	return 0;
>>   err:
>>   	kfree(cxl->cxlds);
>> diff --git a/include/linux/cxl/cxl.h b/include/linux/cxl/cxl.h
>> index 08723b2d75bc..fc0859f841dc 100644
>> --- a/include/linux/cxl/cxl.h
>> +++ b/include/linux/cxl/cxl.h
>> @@ -55,4 +55,6 @@ int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds);
>>   int cxl_request_resource(struct cxl_dev_state *cxlds, enum cxl_resource type);
>>   int cxl_release_resource(struct cxl_dev_state *cxlds, enum cxl_resource type);
>>   void cxl_set_media_ready(struct cxl_dev_state *cxlds);
>> +struct cxl_memdev *devm_cxl_add_memdev(struct device *host,
>> +				       struct cxl_dev_state *cxlds);
>>   #endif

  reply	other threads:[~2024-09-16 12:39 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-07  8:18 [PATCH v3 00/20] cxl: add Type2 device support alejandro.lucero-palau
2024-09-07  8:18 ` [PATCH v3 01/20] cxl: add type2 device basic support alejandro.lucero-palau
2024-09-07 20:26   ` kernel test robot
2024-09-10  6:12   ` Li, Ming4
2024-09-10  7:25     ` Alejandro Lucero Palau
2024-09-12  8:57   ` Zhi Wang
2024-09-16  9:52     ` Alejandro Lucero Palau
2024-09-12  9:35   ` Zhi Wang
2024-09-16 10:03     ` Alejandro Lucero Palau
2024-09-13 16:41   ` Jonathan Cameron
2024-09-16 12:03     ` Alejandro Lucero Palau
2024-09-16 12:24       ` Jonathan Cameron
2024-09-07  8:18 ` [PATCH v3 02/20] cxl: add capabilities field to cxl_dev_state and cxl_port alejandro.lucero-palau
2024-09-07 18:08   ` kernel test robot
2024-09-11 22:17   ` Dave Jiang
2024-09-16  8:36     ` Alejandro Lucero Palau
2024-09-16 16:07       ` Dave Jiang
2024-09-13 17:25   ` Jonathan Cameron
2024-09-16 12:13     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 03/20] cxl/pci: add check for validating capabilities alejandro.lucero-palau
2024-09-10  3:26   ` Li, Ming4
2024-09-10  6:24     ` Li, Ming4
2024-09-10  7:31       ` Alejandro Lucero Palau
2024-09-11 23:06   ` Dave Jiang
2024-09-16  8:56     ` Alejandro Lucero Palau
2024-09-16 16:11       ` Dave Jiang
2024-09-13 17:28   ` Jonathan Cameron
2024-09-16 12:17     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 04/20] cxl: move pci generic code alejandro.lucero-palau
2024-09-11 23:55   ` Dave Jiang
2024-09-16  9:46     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 05/20] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2024-09-10  6:00   ` Li, Ming4
2024-09-10  7:24     ` Alejandro Lucero Palau
2024-09-12  9:08       ` Zhi Wang
2024-09-13 17:32   ` Jonathan Cameron
2024-09-16 12:23     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 06/20] cxl: add functions for resource request/release by a driver alejandro.lucero-palau
2024-09-10  6:15   ` Li, Ming4
2024-09-16  8:15     ` Alejandro Lucero Palau
2024-09-13 17:35   ` Jonathan Cameron
2024-09-16 12:33     ` Alejandro Lucero Palau
2024-09-16 13:21       ` Jonathan Cameron
2024-09-07  8:18 ` [PATCH v3 07/20] cxl: harden resource_contains checks to handle zero size resources alejandro.lucero-palau
2024-09-13 17:36   ` Jonathan Cameron
2024-09-16 12:36     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 08/20] cxl: add function for setting media ready by a driver alejandro.lucero-palau
2024-09-07  8:18 ` [PATCH v3 09/20] cxl: support type2 memdev creation alejandro.lucero-palau
2024-09-12 18:19   ` Dave Jiang
2024-09-16 12:38     ` Alejandro Lucero Palau [this message]
2024-09-07  8:18 ` [PATCH v3 10/20] cxl: indicate probe deferral alejandro.lucero-palau
2024-09-10  6:37   ` Li, Ming4
2024-09-16  8:24     ` Alejandro Lucero Palau
2024-09-17  3:31       ` Li, Ming4
2024-09-17  9:16         ` Alejandro Lucero Palau
2024-09-12  9:19   ` Zhi Wang
2024-09-16 10:08     ` Alejandro Lucero Palau
2024-09-13 17:43   ` Jonathan Cameron
2024-09-16 13:24     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 11/20] cxl: define a driver interface for HPA free space enumaration alejandro.lucero-palau
2024-09-13 17:52   ` Jonathan Cameron
2024-09-16 14:09     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 12/20] efx: use acquire_endpoint when looking for free HPA alejandro.lucero-palau
2024-09-07 19:33   ` kernel test robot
2024-09-12 23:09   ` Dave Jiang
2024-09-16 10:29     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 13/20] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2024-09-13 17:59   ` Jonathan Cameron
2024-09-16 14:26     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 14/20] cxl: make region type based on endpoint type alejandro.lucero-palau
2024-09-07  8:18 ` [PATCH v3 15/20] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2024-09-07  8:18 ` [PATCH v3 16/20] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2024-09-07  8:18 ` [PATCH v3 17/20] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2024-09-13 18:08   ` Jonathan Cameron
2024-09-16 16:31     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 18/20] cxl: preclude device memory to be used for dax alejandro.lucero-palau
2024-09-13 17:26   ` Dave Jiang
2024-09-16 14:32     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 19/20] cxl: add function for obtaining params from a region alejandro.lucero-palau
2024-09-13 17:48   ` Dave Jiang
2024-09-16 16:22     ` Alejandro Lucero Palau
2024-09-07  8:18 ` [PATCH v3 20/20] efx: support pio mapping based on cxl alejandro.lucero-palau
2024-09-13 17:45   ` Edward Cree
2024-09-16 16:12     ` Alejandro Lucero Palau
2024-09-13 17:52   ` Dave Jiang
2024-09-16 16:23     ` Alejandro Lucero Palau
2024-09-13 18:10   ` Jonathan Cameron
2024-09-16 16:23     ` Alejandro Lucero Palau

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