From: Paul Walmsley <pjw@kernel.org>
To: sun.wenhan@zte.com.cn
Cc: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, liu.qingtao2@zte.com.cn,
lv.yating@zte.com.cn, guo.chang2@zte.com.cn,
deng.weixian@zte.com.cn, hu.yuye@zte.com.cn
Subject: Re: [PATCH] riscv: align pcie bus assign logic with ARM64
Date: Fri, 25 Sep 2026 17:46:38 -0600 (MDT) [thread overview]
Message-ID: <c8bd7448-e9f3-72fc-9c91-db0c2525a3a1@kernel.org> (raw)
In-Reply-To: <202609220934.68M9Y2eC015972@mse-db.zte.com.cn>
Hi
On Tue, 22 Sep 2026, sun.wenhan@zte.com.cn wrote:
> RISC-V currently relies on the asm-generic default of
> pcibios_assign_all_busses() returning 1, so the kernel always
> re-assigns all PCI bus numbers and ignores the bus numbers already
> set up by the firmware. This has two downsides:
>
> 1. As UEFI 2.8 has brought mature firmware support to RISC-V servers,
> the OS can trust and inherit the PCI bus enumeration done by the
> BIOS, skipping a redundant re-enumeration at boot and improving
> the boot time.
>
> 2. The unconditional re-assignment causes bus numbering conflicts
> during PCI rescan. When a root port that is not the last one in
> the hierarchy is removed and the bus is rescanned, the kernel
> fails with:
>
> pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under
> [bus 00-ff] (conflicts with (null) [bus 02])
>
> as reported for the same generic code in commit bd8cbe66c01d
> ("PCI: Make PCI bus renumbering configurable to avoid rescan
> conflicts").
>
> Define pcibios_assign_all_busses() the same way as ARM64,
> so that RISC-V also preserves the bus numbers assigned by the
> firmware by default instead of always re-assigning them. This keeps
> RISC-V consistent with the other major architectures.
>
> Signed-off-by: sun wenhan <sun.wenhan@zte.com.cn>
This patch doesn't apply -- see
https://gist.github.com/linux-riscv-bot/4f238956cd137e576af24c32c44d3437
-- and the commit ID mentioned in the patch description doesn't appear to
exist in mainline. Can you please fix these issues and resend?
thanks,
- Paul
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next prev parent reply other threads:[~2026-09-25 23:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-22 9:19 [PATCH] riscv: align pcie bus assign logic with ARM64 sun.wenhan
2026-09-25 23:46 ` Paul Walmsley [this message]
2026-09-29 9:30 ` sun.wenhan
2026-10-05 16:56 ` Paul Walmsley
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