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[201.68.240.180]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fc13ac19aesm8301249a91.17.2025.02.17.08.37.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Feb 2025 08:37:42 -0800 (PST) Message-ID: Date: Mon, 17 Feb 2025 13:37:37 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/riscv: Respect mseccfg.RLB bit for TOR mode PMP entry To: Rob Bradford , qemu-devel@nongnu.org Cc: Palmer Dabbelt , Bin Meng , Weiwei Li , qemu-riscv@nongnu.org, Liu Zhiwei , Alistair Francis References: <20250210153713.343626-1-rbradford@rivosinc.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20250210153713.343626-1-rbradford@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 2/10/25 12:37 PM, Rob Bradford wrote: > When running in TOR mode (Top of Range) the next PMP entry controls > whether the entry is locked. However simply checking if the PMP_LOCK bit > is set is not sufficient with the Smepmp extension which now provides a > bit (mseccfg.RLB (Rule Lock Bypass)) to disregard the lock bits. In > order to respect this bit use the convenience pmp_is_locked() function > rather than directly checking PMP_LOCK since this function checks > mseccfg.RLB. > > Signed-off-by: Rob Bradford > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/pmp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index a185c246d6..85ab270dad 100644 > --- a/target/riscv/pmp.c > +++ b/target/riscv/pmp.c > @@ -524,7 +524,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, > uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg; > is_next_cfg_tor = PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg); > > - if (pmp_cfg & PMP_LOCK && is_next_cfg_tor) { > + if (pmp_is_locked(env, addr_index + 1) && is_next_cfg_tor) { > qemu_log_mask(LOG_GUEST_ERROR, > "ignoring pmpaddr write - pmpcfg + 1 locked\n"); > return;