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([2804:431:c7c7:52e2:fb25:323c:5709:7237]) by smtp.gmail.com with ESMTPSA id b17-20020a4a98d1000000b00440b3e215cesm819747ooj.46.2022.08.03.02.43.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Aug 2022 02:43:20 -0700 (PDT) Message-ID: Date: Wed, 3 Aug 2022 06:43:18 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH 15/19] ppc/ppc405: QOM'ify PLB Content-Language: en-US To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, BALATON Zoltan References: <20220801131039.1693913-1-clg@kaod.org> <20220801131039.1693913-16-clg@kaod.org> From: Daniel Henrique Barboza In-Reply-To: <20220801131039.1693913-16-clg@kaod.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/1/22 10:10, Cédric Le Goater wrote: > Signed-off-by: Cédric Le Goater > --- > hw/ppc/ppc405.h | 14 ++++++++++ > hw/ppc/ppc405_uc.c | 67 +++++++++++++++++++++++++++++++++------------- > 2 files changed, 62 insertions(+), 19 deletions(-) > > diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h > index d39d65cc86e4..4ff5cdcf5c65 100644 > --- a/hw/ppc/ppc405.h > +++ b/hw/ppc/ppc405.h > @@ -65,6 +65,19 @@ struct ppc4xx_bd_info_t { > > typedef struct Ppc405SoCState Ppc405SoCState; > > +/* Peripheral local bus arbitrer */ I wasn't aware that arbitrer is a word. Google says that 'arbitrer' is an old form of 'arbitrator'. I looked it up because I thought you misspelled 'arbiter', which is the name of a Protoss combat unit in Starcraft. And it happens to be a synonym of 'arbitrator' as well. 'arbitrer' is fine, don't worry about it. Reviewed-by: Daniel Henrique Barboza > +#define TYPE_PPC405_PLB "ppc405-plb" > +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB); > +struct Ppc405PlbState { > + DeviceState parent_obj; > + > + PowerPCCPU *cpu; > + > + uint32_t acr; > + uint32_t bear; > + uint32_t besr; > +}; > + > /* PLB to OPB bridge */ > #define TYPE_PPC405_POB "ppc405-pob" > OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB); > @@ -245,6 +258,7 @@ struct Ppc405SoCState { > Ppc405EbcState ebc; > Ppc405OpbaState opba; > Ppc405PobState pob; > + Ppc405PlbState plb; > }; > > /* PowerPC 405 core */ > diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c > index 218d911bca3c..45bcf3a6dd8a 100644 > --- a/hw/ppc/ppc405_uc.c > +++ b/hw/ppc/ppc405_uc.c > @@ -148,19 +148,11 @@ enum { > PLB4A1_ACR = 0x089, > }; > > -typedef struct ppc4xx_plb_t ppc4xx_plb_t; > -struct ppc4xx_plb_t { > - uint32_t acr; > - uint32_t bear; > - uint32_t besr; > -}; > - > static uint32_t dcr_read_plb (void *opaque, int dcrn) > { > - ppc4xx_plb_t *plb; > + Ppc405PlbState *plb = PPC405_PLB(opaque); > uint32_t ret; > > - plb = opaque; > switch (dcrn) { > case PLB0_ACR: > ret = plb->acr; > @@ -182,9 +174,8 @@ static uint32_t dcr_read_plb (void *opaque, int dcrn) > > static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) > { > - ppc4xx_plb_t *plb; > + Ppc405PlbState *plb = PPC405_PLB(opaque); > > - plb = opaque; > switch (dcrn) { > case PLB0_ACR: > /* We don't care about the actual parameters written as > @@ -202,28 +193,55 @@ static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) > } > } > > -static void ppc4xx_plb_reset (void *opaque) > +static void ppc405_plb_reset(DeviceState *dev) > { > - ppc4xx_plb_t *plb; > + Ppc405PlbState *plb = PPC405_PLB(dev); > > - plb = opaque; > plb->acr = 0x00000000; > plb->bear = 0x00000000; > plb->besr = 0x00000000; > } > > -void ppc4xx_plb_init(CPUPPCState *env) > +static void ppc405_plb_realize(DeviceState *dev, Error **errp) > { > - ppc4xx_plb_t *plb; > + Ppc405PlbState *plb = PPC405_PLB(dev); > + CPUPPCState *env; > + > + assert(plb->cpu); > + > + env = &plb->cpu->env; > > - plb = g_new0(ppc4xx_plb_t, 1); > ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); > - qemu_register_reset(ppc4xx_plb_reset, plb); > +} > + > +static Property ppc405_plb_properties[] = { > + DEFINE_PROP_LINK("cpu", Ppc405PlbState, cpu, TYPE_POWERPC_CPU, > + PowerPCCPU *), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void ppc405_plb_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + > + dc->realize = ppc405_plb_realize; > + dc->user_creatable = false; > + dc->reset = ppc405_plb_reset; > + device_class_set_props(dc, ppc405_plb_properties); > +} > + > +void ppc4xx_plb_init(CPUPPCState *env) > +{ > + PowerPCCPU *cpu = env_archcpu(env); > + DeviceState *dev = qdev_new(TYPE_PPC405_EBC); > + > + object_property_set_link(OBJECT(cpu), "cpu", OBJECT(dev), &error_abort); > + qdev_realize_and_unref(dev, NULL, &error_fatal); > } > > /*****************************************************************************/ > @@ -1446,6 +1464,8 @@ static void ppc405_soc_instance_init(Object *obj) > object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA); > > object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB); > + > + object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB); > } > > static void ppc405_soc_realize(DeviceState *dev, Error **errp) > @@ -1492,7 +1512,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp) > } > > /* PLB arbitrer */ > - ppc4xx_plb_init(env); > + object_property_set_link(OBJECT(&s->plb), "cpu", OBJECT(&s->cpu), > + &error_abort); > + if (!qdev_realize(DEVICE(&s->plb), NULL, errp)) { > + return; > + } > > /* PLB to OPB bridge */ > object_property_set_link(OBJECT(&s->pob), "cpu", OBJECT(&s->cpu), > @@ -1617,6 +1641,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data) > > static const TypeInfo ppc405_types[] = { > { > + .name = TYPE_PPC405_PLB, > + .parent = TYPE_DEVICE, > + .instance_size = sizeof(Ppc405PlbState), > + .class_init = ppc405_plb_class_init, > + }, { > .name = TYPE_PPC405_POB, > .parent = TYPE_DEVICE, > .instance_size = sizeof(Ppc405PobState),