From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Richard Acayan <mailingradian@gmail.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Daniel Lezcano <daniel.lezcano@kernel.org>,
Zhang Rui <rui.zhang@intel.com>,
Lukasz Luba <lukasz.luba@arm.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Amit Kucheria <amitk@kernel.org>,
Thara Gopinath <thara.gopinath@gmail.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v3 3/3] arm64: dts: qcom: sdm670: add thermal zones and thermal devices
Date: Tue, 10 Mar 2026 11:57:38 +0100 [thread overview]
Message-ID: <caa23d34-f71e-40f5-b142-dde53e95b6f4@oss.qualcomm.com> (raw)
In-Reply-To: <20260310002037.1863-4-mailingradian@gmail.com>
On 3/10/26 1:20 AM, Richard Acayan wrote:
> Add thermal zones to safeguard from overheating to high temperatures,
> along with the thermal sensors (TSENS) and CPU frequency limits (LMh).
> The temperatures are very high, but should still be safeguard for
> devices that do not specify their own thermal zones.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
[...]
> + tsens0: thermal-sensor@c263000 {
> + compatible = "qcom,sdm670-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c263000 0 0x1ff>,
> + <0 0x0c222000 0 0x4>;
Both regions are 0x1000-long for both controllers
> + interrupts-extended = <&pdc 26 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 28 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "uplow", "critical";
> + #thermal-sensor-cells = <1>;
> + #qcom,sensors = <13>;
> + };
> +
> + tsens1: thermal-sensor@c265000 {
> + compatible = "qcom,sdm670-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c265000 0 0x1ff>,
> + <0 0x0c223000 0 0x4>;
> + interrupts-extended = <&pdc 27 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 29 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "uplow", "critical";
> + #thermal-sensor-cells = <1>;
> + #qcom,sensors = <8>;
> + };
[...]
> + lmh_cluster1: lmh@17d70800 {
> + compatible = "qcom,sdm670-lmh", "qcom,sdm845-lmh";
> + reg = <0 0x17d70800 0 0x400>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
I think you got the interrupt indices backwards (i.e. 32 -> clus0)
Konrad
next prev parent reply other threads:[~2026-03-10 10:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-10 0:20 [PATCH v3 0/3] SDM670 Basic SoC thermal zones Richard Acayan
2026-03-10 0:20 ` [PATCH v3 1/3] dt-bindings: thermal: tsens: add SDM670 compatible Richard Acayan
2026-03-10 0:20 ` [PATCH v3 2/3] dt-bindings: thermal: lmh: Add " Richard Acayan
2026-03-10 8:02 ` Krzysztof Kozlowski
2026-03-10 0:20 ` [PATCH v3 3/3] arm64: dts: qcom: sdm670: add thermal zones and thermal devices Richard Acayan
2026-03-10 10:57 ` Konrad Dybcio [this message]
2026-03-11 2:32 ` Richard Acayan
2026-03-10 10:18 ` [PATCH v3 0/3] SDM670 Basic SoC thermal zones Daniel Lezcano
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