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Fri, 14 Feb 2020 18:26:13 -0800 (PST) Subject: Re: [PATCH 02/10] riscv: Force flat memory model with no-mmu To: Damien Le Moal , "linux-riscv@lists.infradead.org" , Palmer Dabbelt References: <20200212103432.660256-1-damien.lemoal@wdc.com> <20200212103432.660256-3-damien.lemoal@wdc.com> <05106cc4-3d79-7288-cd1f-0c996e5b1657@gmail.com> From: Sean Anderson Autocrypt: addr=seanga2@gmail.com; prefer-encrypt=mutual; keydata= mQENBFe74PkBCACoLC5Zq2gwrDcCkr+EPGsT14bsxrW07GiYzQhLCgwnPdEpgU95pXltbFhw 46GfyffABWxHKO2x+3L1S6ZxC5AiKbYXo7lpnTBYjamPWYouz+VJEVjUx9aaSEByBah5kX6a lKFZWNbXLAJh+dE1HFaMi3TQXXaInaREc+aO1F7fCa2zNE75ja+6ah8L4TPRFZ2HKQzve0/Y GXtoRw97qmnm3U36vKWT/m2AiLF619F4T1mHvlfjyd9hrVwjH5h/2rFyroXVXBZHGA9Aj8eN F2si35dWSZlIwXkNu9bXp0/pIu6FD0bI+BEkD5S7aH1G1iAcMFi5Qq2RNa041DfQSDDHABEB AAG0K1NlYW4gR2FsbGFnaGVyIEFuZGVyc29uIDxzZWFuZ2EyQGdtYWlsLmNvbT6JAVcEEwEK AEECGwMFCwkIBwIGFQgJCgsCBBYCAwECHgECF4ACGQEWIQSQYR1bzo1I0gPoYCg+6I/stKEQ bgUCXT+S2AUJB2TlXwAKCRA+6I/stKEQbhNOB/9ooea0hU9Sgh7PBloU6CgaC5mlqPLB7NTp +JkB+nh3Fqhk+qLZwzEynnuDLl6ESpVHIc0Ym1lyF4gT3DsrlGT1h0Gzw7vUwd1+ZfN0CuIx Rn861U/dAUjvbtN5kMBqOI4/5ea+0r7MACcIVnKF/wMXBD8eypHsorT2sJTzwZ6DRCNP70C5 N1ahpqqNmXe0uLdP0pu55JCqhrGw2SinkRMdWyhSxT56uNwIVHGhLTqH7Q4t1N6G1EH626qa SvIJsWlNpll6Y3AYLDw2/Spw/hqieS2PQ/Ky3rPZnvJt7/aSNYsKoFGX0yjkH67Uq8Lx0k1L w8jpXnbEPQN3A2ZJCbeMuQENBF0/k2UBCADhvSlHblNc/aRAWtCFDblCJJMN/8Sd7S9u4ZRS w1wIB4tTF7caxc8yfCHa+FjMFeVu34QPtMOvd/gfHz0mr+t0PiTAdDSbd6o7tj+g5ylm+FhT OTUtJQ6mx6L9GzMmIDEbLxJMB9RfJaL2mT5JkujKxEst6nlHGV/lEQ54xBl5ImrPvuR5Dbnr zWQYlafb1IC5ZFwSMpBeSfhS7/kGPtFY3NkpLrii/CF+ME0DYYWxlkDIycqF3fsUGGfb3HIq z2l95OB45+mCs9DrIDZXRT6mFjLcl35UzuEErNIskCl9NKlbvAMAl+gbDH275SnE44ocC4qu 0tMe7Z5jpOy6J8nNABEBAAGJATwEGAEKACYWIQSQYR1bzo1I0gPoYCg+6I/stKEQbgUCXT+T ZQIbDAUJAeEzgAAKCRA+6I/stKEQbjAGB/4mYRqZTTEFmcS+f+8zsmjt2CfWvm38kR+sJFWB vz82pFiUWbUM5xvcuOQhz698WQnIazbDGSYaOipyVNS52YiuYJDqMszzgw++DrcSuu0oRYWN EWCkJjxMqjGg8uY0OZ6FJG+gYRN5wMFErGfV1OqQ7l00FYA9OzpOEuW9PzPZEutFnAbbh77i zvxbQtT7IJCL24A4KutNYKmWg98im4mCzQcJCxE86Bv69ErLVPUyYbp4doLadScilXlvkkjL iq1wOt3rRzOuw+qnWVgWGBPxdDftz0Wck941tYF9XE0aMgkf4o1sGoDZFUFPCQdfEYPzzV7O S5hN3/mP5UeooFHb Message-ID: Date: Fri, 14 Feb 2020 21:26:12 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200214_182615_544164_6DC9A230 X-CRM114-Status: GOOD ( 21.52 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Paul Walmsley Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 2/14/20 9:15 PM, Damien Le Moal wrote: > On 2020/02/15 5:18, Sean Anderson wrote: >> Hi, >> >> On 2/12/20 5:34 AM, Damien Le Moal wrote: >>> Compilation errors trigger if ARCH_SPARSEMEM_ENABLE is enabled for >>> a nommu kernel. Since the sparsemem model does not make sense anyway >>> for the nommu case, do not allow selecting this option to always use >>> the flatmem model. >>> >>> Signed-off-by: Damien Le Moal >>> --- >>> arch/riscv/Kconfig | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >>> index 73f029eae0cc..1a3b5a5276be 100644 >>> --- a/arch/riscv/Kconfig >>> +++ b/arch/riscv/Kconfig >>> @@ -121,6 +121,7 @@ config ARCH_FLATMEM_ENABLE >>> >>> config ARCH_SPARSEMEM_ENABLE >>> def_bool y >>> + depends on MMU >>> select SPARSEMEM_VMEMMAP_ENABLE >>> >>> config ARCH_SELECT_MEMORY_MODEL >>> >> >> Just for some background, why did you choose NOMMU? Afaik the K210 has >> an MMU following the RISC-V privileged specification 1.9 > > Our early experiments with the k210 with opensbi revealed that the mmu is > definitely not a normal one or that it is not functional (e.g. S-mode fault > delegation bit setup leads to a hang). So at the time, we started assuming > that this is a nommu platform. > > Since then, others also mentioned that there is in fact an MMU but not > following the latest specs (I think Olof mentioned that). But I have not > look into this (yet) to try to make it work. Not sure how much effort would > be needed on the kernel to support this older specs mmu. > > In any case, considering the tiny 6+2MB of memory available, direct M-mode > Linux boot avoids the bootloader chain and openSBI use, which saves a lot > of memory. We could reduce this chain to opensbi with direct payload only, > but even then, page alignment will lead to memory loss. And at run-time, > nommu saves a lot too with the absence of page tables. Nommu makes sense > for this platform. Well, the VM mode bits are in mstatus for this priv spec, so OpenSBI won't work since there is no way to set them. > > This is the first step to get this platform running Linux. Due to the low > memory, it probably isn't a practical use case to use Linux in the first > place, but it definitely is a great inexpensive platform for getting > started with RISCV. NOMMU allows running Linux without much effort. Going > forward, we can also try to get that SoC MMU running. Yeah, that's pretty reasonable. However, I don't think much has changed other than the locations of some of the registers has been changed around. The existing code to set up page table entries should not need major modifications. Alternatively, the base+bound scheme could probably work pretty well with low memory, though we would not be able to re-use any existing code. --Sean