Re: [Intel-gfx] [PATCH 2/4] drm/i915/dg2: Add support for DG2 render and media compression

[Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On 4.4.2022 16.38, Imre Deak wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Add support for DG2 render and media compression, for the description of
> buffer layouts see the previous patch adding the corresponding
> frame buffer modifiers.
> 
> v2:
>    Display version fix [Imre]
> v3:
>    Split out modifier addition to separate patch.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_fb.c       | 13 ++++++++++
>   .../drm/i915/display/skl_universal_plane.c    | 26 ++++++++++++++++---
>   2 files changed, 35 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index e9ad142ac40fa..447003a91160e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -141,6 +141,14 @@ struct intel_modifier_desc {
>   
>   static const struct intel_modifier_desc intel_modifiers[] = {
>   	{
> +		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> +		.display_ver = { 13, 13 },
> +		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
> +	}, {
> +		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> +		.display_ver = { 13, 13 },
> +		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
> +	}, {
>   		.modifier = I915_FORMAT_MOD_4_TILED,
>   		.display_ver = { 13, 13 },
>   		.plane_caps = INTEL_PLANE_CAP_TILING_4,
> @@ -550,6 +558,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>   			return 128;
>   		else
>   			return 512;
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>   	case I915_FORMAT_MOD_4_TILED:
>   		/*
>   		 * Each 4K tile consists of 64B(8*8) subtiles, with
> @@ -752,6 +762,9 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>   	case I915_FORMAT_MOD_4_TILED:
>   	case I915_FORMAT_MOD_Yf_TILED:
>   		return 1 * 1024 * 1024;
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> +		return 16 * 1024;
>   	default:
>   		MISSING_CASE(fb->modifier);
>   		return 0;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index c57fca1fe6788..b939c503bc6ff 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -773,6 +773,14 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>   		return PLANE_CTL_TILED_Y;
>   	case I915_FORMAT_MOD_4_TILED:
>   		return PLANE_CTL_TILED_4;
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +		return PLANE_CTL_TILED_4 |
> +			PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> +			PLANE_CTL_CLEAR_COLOR_DISABLE;
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> +		return PLANE_CTL_TILED_4 |
> +			PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
> +			PLANE_CTL_CLEAR_COLOR_DISABLE;
>   	case I915_FORMAT_MOD_Y_TILED_CCS:
>   	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>   		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -2168,6 +2176,10 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
>   	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
>   		return false;
>   
> +	/* Wa_14013215631 */
> +	if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> +		return false;
> +
>   	return plane_id < PLANE_SPRITE4;
>   }
>   
> @@ -2415,9 +2427,10 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
>   	case PLANE_CTL_TILED_Y:
>   		plane_config->tiling = I915_TILING_Y;
>   		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> -			fb->modifier = DISPLAY_VER(dev_priv) >= 12 ?
> -				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> -				I915_FORMAT_MOD_Y_TILED_CCS;
> +			if (DISPLAY_VER(dev_priv) >= 12)
> +				fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> +			else
> +				fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
>   		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
>   			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
>   		else
> @@ -2425,7 +2438,12 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
>   		break;
>   	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
>   		if (HAS_4TILE(dev_priv)) {
> -			fb->modifier = I915_FORMAT_MOD_4_TILED;
> +			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> +				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
> +			else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> +				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
> +			else
> +				fb->modifier = I915_FORMAT_MOD_4_TILED;
>   		} else {
>   			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
>   				fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;