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boundary="------------jKccWE9fJ6LvFeqP9TmJXlzP" Message-ID: Date: Wed, 17 Jun 2026 11:24:53 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/9] qtest/phb4: Add testbench for PHB4 To: Harsh Prateek Bora , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, danielhb413@gmail.com, Michael Kowal , chalapathi.v@linux.ibm.com, Caleb Schlossin , Glenn Miles , jishnuvw@linux.ibm.com, Aditya Gupta , amachhiw@linux.ibm.com References: <20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com> <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> <20260305060923.3753402-2-saif.abrar@linux.vnet.ibm.com> Content-Language: en-US From: Saif Abrar In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDA1MSBTYWx0ZWRfX8835IGC+gbKv Hx+4gjPMFmZ2lDry111Zr6HHiWICiwg6/7SwBHu5JEH27mHlaYpF4V3CoSZVlhDaItZVBxkcIW2 9wak8CXTLiTlypKp1XNuw2sgc4ypvMs= X-Proofpoint-ORIG-GUID: rKxS6I2HWY45c1X9aGlZkqHaoDrcqh5I X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDA1MSBTYWx0ZWRfX8uEc9YYshv79 jJfAibD5Sg1dnVBpPogw0IZG4MH7EiOgL0puFPhgIJz6m4nP96K1kqYxm0KLtH4y6nDuPf2xX64 hML4f7CH7n5N49zVqK82dArf9qO8lrao8D/AnX8HruHO4Xx3/+krG+1f81BZlHjayndzoDwdz9O 7UZH/N0/uu3sDzelFrC1fIwVM3qFguoWy2YvOP7sm20dcUrkBmbS+ZTmuUQAvDNb3jzHcNYJNdI 4hvgWgFwFfdJWTeON5ciZ3Y3MEy5k/2HuYXWMFUSuB4SGhwOhJzUw0zILsh/v+mFYaAMLseHfpJ nKY7AuvzTmrxTjdUeSTQesrng+SN0PaMOKNAkpur3bFZavz6WVyPpLB47YqvZQyMvb8vTlfxOqu 9OBfIlqDAi3Nl7FiY/sHriBMyQZ4pxeBAO4p55HD38LE0GLPototJYdgjUApPu7UUxbPBSmWYXK FneDIfhOKeRS1XiY7UQ== X-Proofpoint-GUID: RV7GhyJ8Iik8bO_lcKvralIDqwzW3EvL X-Authority-Analysis: v=2.4 cv=L9gtheT8 c=1 sm=1 tr=0 ts=6a3236bb cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=r77TgQKjGQsHNAKrUKIA:9 a=VnNF1IyMAAAA:8 a=aow-egSQAAAA:8 a=j2bEz6JK-_-10P5Y8ywA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PrhnCPEB6Ue097zCAmMA:9 a=_P4aAJQNgKZvbp30:21 a=_W_S_7VecoQA:10 a=lqcHg5cX4UMA:10 a=gFNbaldVC-z-bsjSTzMo:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-16_05,2026-06-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 malwarescore=0 clxscore=1011 adultscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606170051 Received-SPF: pass client-ip=148.163.156.1; envelope-from=saif.abrar@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 17 Jun 2026 02:22:58 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This is a multi-part message in MIME format. --------------jKccWE9fJ6LvFeqP9TmJXlzP Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 01-05-2026 19:29, Harsh Prateek Bora wrote: > > > On 05/03/26 11:39 am, Saif Abrar wrote: >> New qtest testbench added for PHB[345]. >> Testbench reads PHB Version register and asserts that >> bits[24:31] have value 0xA3, 0xA4 and 0xA5 respectively. >> >> Signed-off-by: Saif Abrar >> Reviewed-by: Cédric Le Goater >> --- >> v3: Updates for coding guidelines. >> v2: Added version check for PHB3 and PHB4 also. >> >>   tests/qtest/meson.build     |  1 + >>   tests/qtest/pnv-phb4-test.c | 98 +++++++++++++++++++++++++++++++++++++ >>   2 files changed, 99 insertions(+) >>   create mode 100644 tests/qtest/pnv-phb4-test.c >> >> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build >> index ba9f59d2f8..030f3f4fc6 100644 >> --- a/tests/qtest/meson.build >> +++ b/tests/qtest/meson.build >> @@ -182,6 +182,7 @@ qtests_ppc64 = \ >>     (config_all_devices.has_key('CONFIG_POWERNV') ? >> ['pnv-xive2-test'] : []) +                 \ >>     (config_all_devices.has_key('CONFIG_POWERNV') ? >> ['pnv-spi-seeprom-test'] : []) +           \ >>     (config_all_devices.has_key('CONFIG_POWERNV') ? >> ['pnv-host-i2c-test'] : []) +              \ >> +  (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-phb4-test'] >> : []) +                  \ > > Should we just call it pnv-phb-test as it takes care of all PHB 3/4/5. Renamed to 'pnv-phb-test'. > > Also, need to audit all the patches whether to keep the naming as just > phb or phb{3,4,5} as applicable. > > >> (config_all_devices.has_key('CONFIG_PSERIES') ? ['numa-test'] : []) >> +                      \ >>     (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : >> []) +                      \ >>     (slirp.found() ? ['pxe-test'] : []) +              \ >> diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c >> new file mode 100644 >> index 0000000000..797f6b6c87 >> --- /dev/null >> +++ b/tests/qtest/pnv-phb4-test.c >> @@ -0,0 +1,98 @@ >> +/* >> + * QTest testcase for PowerNV PHB4 >> + * >> + * Copyright (c) 2025, IBM Corporation. >> + * >> + * SPDX-License-Identifier: GPL-2.0-or-later >> + * >> + */ >> + >> +#include "qemu/osdep.h" >> +#include "libqtest.h" >> +#include "hw/pci-host/pnv_phb4_regs.h" >> +#include "pnv-xscom.h" >> + >> +#define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit)) >> +#define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | >> PPC_BIT(bs)) > > Looks like we already have 2 files in tests/qtest folder which > contains these macros. Time to cleanup common code into a common header ? Common code moved to a new common header file 'tests/qtest/pnv-qtest-common.h'. >> + >> +#define PHB3_PBCQ_SPCI_ASB_ADDR      0x0 >> +#define PHB3_PBCQ_SPCI_ASB_DATA      0x2 >> + >> +/* Index of PNV_CHIP_POWER10 in pnv_chips[] within "pnv-xscom.h" */ >> +#define PNV_P10_CHIP_INDEX      3 > > Where is this being used and do we really need it? Removed, not used in this patch. > >> +#define PHB4_XSCOM 0x40084800ull >> + >> +/* >> + * Indirect XSCOM read:: >> + * - Write 'Indirect Address Register' with register-offset to read. >> + * - Read 'Indirect Data Register' to get the value. >> + */ >> +static uint64_t pnv_phb_xscom_read(QTestState *qts, const PnvChip >> *chip, >> +        uint64_t scom, uint32_t indirect_addr, uint32_t indirect_data, >> +        uint64_t reg) >> +{ >> +    qtest_writeq(qts, pnv_xscom_addr(chip, (scom >> 3) + >> indirect_addr), reg); > > What does bit shift 3 signify here, can we have a self explanatory > macro for this? Added a macro for SCOM to PCBA address conversion. > >> +    return qtest_readq(qts, pnv_xscom_addr(chip, (scom >> 3) + >> indirect_data)); >> +} >> + >> +/* Assert that 'PHB - Version Register' bits[24:31] are as expected */ >> +static void phb_version_test(const void *data) >> +{ >> +    const PnvChip *chip = (PnvChip *)data; >> +    QTestState *qts; >> +    const char *machine = "powernv8"; >> +    uint64_t phb_xscom = 0x4809e000; >> +    uint64_t reg_phb_version = PHB_VERSION; >> +    uint32_t indirect_addr = PHB3_PBCQ_SPCI_ASB_ADDR; >> +    uint32_t indirect_data = PHB3_PBCQ_SPCI_ASB_DATA; >> +    uint32_t expected_ver = 0xA3; >> +    uint64_t ver; >> + >> +    if (chip->chip_type == PNV_CHIP_POWER9) { >> +        machine = "powernv9"; >> +        phb_xscom = 0x68084800; >> +        indirect_addr = PHB_SCOM_HV_IND_ADDR; >> +        indirect_data = PHB_SCOM_HV_IND_DATA; >> +        reg_phb_version |= PPC_BIT(0); >> +        expected_ver = 0xA4; >> +    } else if (chip->chip_type == PNV_CHIP_POWER10) { > > What about POWER11? Also, could the check be based on PHB type supported > (need new attribute?) so that we dont need to add checks for every next > PnvChip->chip_type which supports the existing PHB type? POWER11 used the same PHB5 as POWER10. If it's decided then the new attribute can be added in future in a new patchset. > >> +        machine = "powernv10"; >> +        phb_xscom = PHB4_XSCOM; >> +        indirect_addr = PHB_SCOM_HV_IND_ADDR; >> +        indirect_data = PHB_SCOM_HV_IND_DATA; >> +        reg_phb_version |= PPC_BIT(0); >> +        expected_ver = 0xA5; >> +    } >> + >> +    qts = qtest_initf("-M %s -accel tcg -cpu %s", machine, >> chip->cpu_model); >> + >> +    ver = pnv_phb_xscom_read(qts, chip, phb_xscom, >> +                                indirect_addr, indirect_data, >> reg_phb_version); >> + >> +    /* PHB Version register bits [24:31] */ >> +    ver = ver >> (63 - 31); > > It is always preferable to mask the remaining bits before extracting. Updated. > >> +    g_assert_cmpuint(ver, ==, expected_ver); >> + >> +    qtest_quit(qts); >> +} >> + >> +/* Verify versions of all supported PHB's */ >> +static void add_phbX_version_test(void) >> +{ >> +    for (int i = 0; i < ARRAY_SIZE(pnv_chips); i++) { >> +        char *tname = g_strdup_printf("pnv-phb/%s", >> +                                      pnv_chips[i].cpu_model); >> +        qtest_add_data_func(tname, &pnv_chips[i], phb_version_test); >> +        g_free(tname); >> +    } >> +} >> + >> +int main(int argc, char **argv) >> +{ >> +    g_test_init(&argc, &argv, NULL); >> + >> +    /* PHB[345] tests */ >> +    add_phbX_version_test(); >> + >> +    return g_test_run(); >> +} > --------------jKccWE9fJ6LvFeqP9TmJXlzP Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit


On 01-05-2026 19:29, Harsh Prateek Bora wrote:
<Adding folks working in this area or who might be interested in it>

On 05/03/26 11:39 am, Saif Abrar wrote:
New qtest testbench added for PHB[345].
Testbench reads PHB Version register and asserts that
bits[24:31] have value 0xA3, 0xA4 and 0xA5 respectively.

Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
v3: Updates for coding guidelines.
v2: Added version check for PHB3 and PHB4 also.

  tests/qtest/meson.build     |  1 +
  tests/qtest/pnv-phb4-test.c | 98 +++++++++++++++++++++++++++++++++++++
  2 files changed, 99 insertions(+)
  create mode 100644 tests/qtest/pnv-phb4-test.c

diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index ba9f59d2f8..030f3f4fc6 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -182,6 +182,7 @@ qtests_ppc64 = \
    (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xive2-test'] : []) +                 \
    (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-spi-seeprom-test'] : []) +           \
    (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-host-i2c-test'] : []) +              \
+  (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-phb4-test'] : []) +                  \

Should we just call it pnv-phb-test as it takes care of all PHB 3/4/5.


Renamed to 'pnv-phb-test'.



Also, need to audit all the patches whether to keep the naming as just phb or phb{3,4,5} as applicable.


    (config_all_devices.has_key('CONFIG_PSERIES') ? ['numa-test'] : []) +                      \
    (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) +                      \
    (slirp.found() ? ['pxe-test'] : []) +              \
diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c
new file mode 100644
index 0000000000..797f6b6c87
--- /dev/null
+++ b/tests/qtest/pnv-phb4-test.c
@@ -0,0 +1,98 @@
+/*
+ * QTest testcase for PowerNV PHB4
+ *
+ * Copyright (c) 2025, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+#include "hw/pci-host/pnv_phb4_regs.h"
+#include "pnv-xscom.h"
+
+#define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
+#define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))

Looks like we already have 2 files in tests/qtest folder which contains these macros. Time to cleanup common code into a common header ?


Common code moved to a new common header file 'tests/qtest/pnv-qtest-common.h'.


+
+#define PHB3_PBCQ_SPCI_ASB_ADDR      0x0
+#define PHB3_PBCQ_SPCI_ASB_DATA      0x2
+
+/* Index of PNV_CHIP_POWER10 in pnv_chips[] within "pnv-xscom.h" */
+#define PNV_P10_CHIP_INDEX      3

Where is this being used and do we really need it?


Removed, not used in this patch.



+#define PHB4_XSCOM              0x40084800ull
+
+/*
+ * Indirect XSCOM read::
+ * - Write 'Indirect Address Register' with register-offset to read.
+ * - Read 'Indirect Data Register' to get the value.
+ */
+static uint64_t pnv_phb_xscom_read(QTestState *qts, const PnvChip *chip,
+        uint64_t scom, uint32_t indirect_addr, uint32_t indirect_data,
+        uint64_t reg)
+{
+    qtest_writeq(qts, pnv_xscom_addr(chip, (scom >> 3) + indirect_addr), reg);

What does bit shift 3 signify here, can we have a self explanatory macro for this?


Added a macro for SCOM to PCBA address conversion.


+    return qtest_readq(qts, pnv_xscom_addr(chip, (scom >> 3) + indirect_data));
+}
+
+/* Assert that 'PHB - Version Register' bits[24:31] are as expected */
+static void phb_version_test(const void *data)
+{
+    const PnvChip *chip = (PnvChip *)data;
+    QTestState *qts;
+    const char *machine = "powernv8";
+    uint64_t phb_xscom = 0x4809e000;
+    uint64_t reg_phb_version = PHB_VERSION;
+    uint32_t indirect_addr = PHB3_PBCQ_SPCI_ASB_ADDR;
+    uint32_t indirect_data = PHB3_PBCQ_SPCI_ASB_DATA;
+    uint32_t expected_ver = 0xA3;
+    uint64_t ver;
+
+    if (chip->chip_type == PNV_CHIP_POWER9) {
+        machine = "powernv9";
+        phb_xscom = 0x68084800;
+        indirect_addr = PHB_SCOM_HV_IND_ADDR;
+        indirect_data = PHB_SCOM_HV_IND_DATA;
+        reg_phb_version |= PPC_BIT(0);
+        expected_ver = 0xA4;
+    } else if (chip->chip_type == PNV_CHIP_POWER10) {

What about POWER11? Also, could the check be based on PHB type supported
(need new attribute?) so that we dont need to add checks for every next
PnvChip->chip_type which supports the existing PHB type?


POWER11 used the same PHB5 as POWER10.

If it's decided then the new attribute can be added in future in a new patchset.



+        machine = "powernv10";
+        phb_xscom = PHB4_XSCOM;
+        indirect_addr = PHB_SCOM_HV_IND_ADDR;
+        indirect_data = PHB_SCOM_HV_IND_DATA;
+        reg_phb_version |= PPC_BIT(0);
+        expected_ver = 0xA5;
+    }
+
+    qts = qtest_initf("-M %s -accel tcg -cpu %s", machine, chip->cpu_model);
+
+    ver = pnv_phb_xscom_read(qts, chip, phb_xscom,
+                                indirect_addr, indirect_data, reg_phb_version);
+
+    /* PHB Version register bits [24:31] */
+    ver = ver >> (63 - 31);

It is always preferable to mask the remaining bits before extracting.


Updated.



+    g_assert_cmpuint(ver, ==, expected_ver);
+
+    qtest_quit(qts);
+}
+
+/* Verify versions of all supported PHB's */
+static void add_phbX_version_test(void)
+{
+    for (int i = 0; i < ARRAY_SIZE(pnv_chips); i++) {
+        char *tname = g_strdup_printf("pnv-phb/%s",
+                                      pnv_chips[i].cpu_model);
+        qtest_add_data_func(tname, &pnv_chips[i], phb_version_test);
+        g_free(tname);
+    }
+}
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+
+    /* PHB[345] tests */
+    add_phbX_version_test();
+
+    return g_test_run();
+}

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