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From: Terry Bowman <Terry.Bowman@amd.com>
To: Dan Williams <dan.j.williams@intel.com>,
	alison.schofield@intel.com, vishal.l.verma@intel.com,
	ira.weiny@intel.com, bwidawsk@kernel.org, dave.jiang@intel.com,
	Jonathan.Cameron@huawei.com, linux-cxl@vger.kernel.org
Cc: rrichter@amd.com, linux-kernel@vger.kernel.org, bhelgaas@google.com
Subject: Re: [PATCH v5 05/26] cxl/core/regs: Add @dev to cxl_register_map
Date: Thu, 8 Jun 2023 16:50:10 -0500	[thread overview]
Message-ID: <cd2a2139-58f2-d863-ce60-2da09948e825@amd.com> (raw)
In-Reply-To: <64822c1c56568_1433ac294db@dwillia2-xfh.jf.intel.com.notmuch>

Thanks Dan. I'll make the changes you mention below.

Regards,
Terry

On 6/8/23 14:29, Dan Williams wrote:
> Terry Bowman wrote:
>> From: Robert Richter <rrichter@amd.com>
>>
>> The corresponding device of a register mapping is used for devm
>> operations and logging. For operations with struct cxl_register_map
>> the device needs to be kept track separately. To simpify the involved
>> function interfaces, add @dev to cxl_register_map.
>>
>> While at it also reorder function arguments of cxl_map_device_regs()
>> and cxl_map_component_regs() to have the object @cxl_register_map
>> first.
>>
>> In a result a bunch of functions are available to be used with a
>> @cxl_register_map object.
>>
>> This patch is in preparation of reworking the component register setup
>> code.
> 
> Looks good to me some small formatting requests below:
> 
>>
>> Signed-off-by: Robert Richter <rrichter@amd.com>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
>> ---
>>  drivers/cxl/core/hdm.c  |  4 ++--
>>  drivers/cxl/core/regs.c | 16 +++++++++++-----
>>  drivers/cxl/cxl.h       | 10 ++++++----
>>  drivers/cxl/pci.c       | 24 ++++++++++++------------
>>  4 files changed, 31 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
>> index 7889ff203a34..5abfa9276dac 100644
>> --- a/drivers/cxl/core/hdm.c
>> +++ b/drivers/cxl/core/hdm.c
>> @@ -85,6 +85,7 @@ static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
>>  				struct cxl_component_regs *regs)
>>  {
>>  	struct cxl_register_map map = {
>> +		.dev = &port->dev,
>>  		.resource = port->component_reg_phys,
>>  		.base = crb,
>>  		.max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
>> @@ -97,8 +98,7 @@ static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
>>  		return -ENODEV;
>>  	}
>>  
>> -	return cxl_map_component_regs(&port->dev, regs, &map,
>> -				      BIT(CXL_CM_CAP_CAP_ID_HDM));
>> +	return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
>>  }
>>  
>>  static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
>> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
>> index c2e6ec6e716d..3b4e56fb36a8 100644
>> --- a/drivers/cxl/core/regs.c
>> +++ b/drivers/cxl/core/regs.c
>> @@ -199,9 +199,11 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
>>  	return ret_val;
>>  }
>>  
>> -int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs,
>> -			   struct cxl_register_map *map, unsigned long map_mask)
>> +int cxl_map_component_regs(struct cxl_register_map *map,
>> +			   struct cxl_component_regs *regs,
>> +			   unsigned long map_mask)
>>  {
>> +	struct device *dev = map->dev;
>>  	struct mapinfo {
>>  		struct cxl_reg_map *rmap;
>>  		void __iomem **addr;
>> @@ -231,10 +233,10 @@ int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs,
>>  }
>>  EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL);
>>  
>> -int cxl_map_device_regs(struct device *dev,
>> -			struct cxl_device_regs *regs,
>> -			struct cxl_register_map *map)
>> +int cxl_map_device_regs(struct cxl_register_map *map,
>> +			struct cxl_device_regs *regs)
>>  {
>> +	struct device *dev = map->dev;
>>  	resource_size_t phys_addr = map->resource;
>>  	struct mapinfo {
>>  		struct cxl_reg_map *rmap;
>> @@ -302,7 +304,10 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
>>  	u32 regloc_size, regblocks;
>>  	int regloc, i;
>>  
>> +	memset(map, 0, sizeof(*map));
>> +	map->dev = &pdev->dev;
>>  	map->resource = CXL_RESOURCE_NONE;
> 
> Use a designated initializer here like other locations:
> 
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 9230b419988e..bd955fae65cd 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -304,9 +304,10 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
>         u32 regloc_size, regblocks;
>         int regloc, i;
>  
> -       memset(map, 0, sizeof(*map));
> -       map->dev = &pdev->dev;
> -       map->resource = CXL_RESOURCE_NONE;
> +       *map = (struct cxl_register_map) {
> +               .dev = &pdev->dev,
> +               .resource = CXL_RESOURCE_NONE,
> +       };
>  
>         regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL,
>                                            CXL_DVSEC_REG_LOCATOR);
> 
>> +
> 
> Remove this unrelated whitespace change.
> 
>>  	regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL,
>>  					   CXL_DVSEC_REG_LOCATOR);
>>  	if (!regloc)
>> @@ -328,6 +333,7 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
>>  	}
>>  
>>  	map->resource = CXL_RESOURCE_NONE;
>> +
> 
> ...and this one too, before Jonathan notices.
> 
>>  	return -ENODEV;
>>  }
>>  EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index a8bda2c74a85..095b767c21e9 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -231,6 +231,7 @@ struct cxl_device_reg_map {
>>  
>>  /**
>>   * struct cxl_register_map - DVSEC harvested register block mapping parameters
>> + * @dev: device for devm operations and logging
>>   * @base: virtual base of the register-block-BAR + @block_offset
>>   * @resource: physical resource base of the register block
>>   * @max_size: maximum mapping size to perform register search
>> @@ -239,6 +240,7 @@ struct cxl_device_reg_map {
>>   * @device_map: cxl_reg_maps for device registers
>>   */
>>  struct cxl_register_map {
>> +	struct device *dev;
>>  	void __iomem *base;
>>  	resource_size_t resource;
>>  	resource_size_t max_size;
>> @@ -253,11 +255,11 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
>>  			      struct cxl_component_reg_map *map);
>>  void cxl_probe_device_regs(struct device *dev, void __iomem *base,
>>  			   struct cxl_device_reg_map *map);
>> -int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs,
>> -			   struct cxl_register_map *map,
>> +int cxl_map_component_regs(struct cxl_register_map *map,
>> +			   struct cxl_component_regs *regs,
>>  			   unsigned long map_mask);
>> -int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs,
>> -			struct cxl_register_map *map);
>> +int cxl_map_device_regs(struct cxl_register_map *map,
>> +			struct cxl_device_regs *regs);
>>  
>>  enum cxl_regloc_type;
>>  int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
>> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
>> index 0872f2233ed0..9c1b44f42e49 100644
>> --- a/drivers/cxl/pci.c
>> +++ b/drivers/cxl/pci.c
>> @@ -274,9 +274,9 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds)
>>  	return 0;
>>  }
>>  
>> -static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map)
>> +static int cxl_map_regblock(struct cxl_register_map *map)
>>  {
>> -	struct device *dev = &pdev->dev;
>> +	struct device *dev = map->dev;
>>  
>>  	map->base = ioremap(map->resource, map->max_size);
>>  	if (!map->base) {
>> @@ -285,21 +285,21 @@ static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map)
>>  	}
>>  
>>  	dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource);
>> +
> 
> Ditto.
> 
>>  	return 0;
>>  }
>>  
>> -static void cxl_unmap_regblock(struct pci_dev *pdev,
>> -			       struct cxl_register_map *map)
>> +static void cxl_unmap_regblock(struct cxl_register_map *map)
>>  {
>>  	iounmap(map->base);
>>  	map->base = NULL;
>>  }
>>  
>> -static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *map)
>> +static int cxl_probe_regs(struct cxl_register_map *map)
>>  {
>>  	struct cxl_component_reg_map *comp_map;
>>  	struct cxl_device_reg_map *dev_map;
>> -	struct device *dev = &pdev->dev;
>> +	struct device *dev = map->dev;
>>  	void __iomem *base = map->base;
>>  
>>  	switch (map->reg_type) {
>> @@ -346,12 +346,12 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>>  	if (rc)
>>  		return rc;
>>  
>> -	rc = cxl_map_regblock(pdev, map);
>> +	rc = cxl_map_regblock(map);
>>  	if (rc)
>>  		return rc;
>>  
>> -	rc = cxl_probe_regs(pdev, map);
>> -	cxl_unmap_regblock(pdev, map);
>> +	rc = cxl_probe_regs(map);
>> +	cxl_unmap_regblock(map);
>>  
>>  	return rc;
>>  }
>> @@ -688,7 +688,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>>  	if (rc)
>>  		return rc;
>>  
>> -	rc = cxl_map_device_regs(&pdev->dev, &cxlds->regs.device_regs, &map);
>> +	rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs);
>>  	if (rc)
>>  		return rc;
>>  
>> @@ -703,8 +703,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>>  
>>  	cxlds->component_reg_phys = map.resource;
>>  
>> -	rc = cxl_map_component_regs(&pdev->dev, &cxlds->regs.component,
>> -				    &map, BIT(CXL_CM_CAP_CAP_ID_RAS));
>> +	rc = cxl_map_component_regs(&map, &cxlds->regs.component,
>> +				    BIT(CXL_CM_CAP_CAP_ID_RAS));
>>  	if (rc)
>>  		dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
>>  
>> -- 
>> 2.34.1
>>
> 
> 
> 

  reply	other threads:[~2023-06-08 21:50 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-07 22:16 [PATCH v5 00/26] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-07 22:16 ` [PATCH v5 01/26] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-08  1:03   ` Dan Williams
2023-06-08  1:11     ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 02/26] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-08  4:53   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 03/26] cxl: Rename member @dport of struct cxl_dport to @dev Terry Bowman
2023-06-08  6:42   ` Dan Williams
2023-06-08 14:36     ` Terry Bowman
2023-06-08 19:08       ` Dan Williams
2023-06-08 19:22         ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 04/26] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-06-08  6:47   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 05/26] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-08 19:29   ` Dan Williams
2023-06-08 21:50     ` Terry Bowman [this message]
2023-06-07 22:16 ` [PATCH v5 06/26] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-08 19:57   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 07/26] cxl/acpi: Moving add_host_bridge_uport() around Terry Bowman
2023-06-08 20:02   ` Dan Williams
2023-06-08 21:50     ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 08/26] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-09  4:24   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 09/26] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-10  0:18   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 10/26] cxl/mem: Prepare for early RCH dport component register setup Terry Bowman
2023-06-10  0:26   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 11/26] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-10  1:36   ` Dan Williams
2023-06-10  1:44   ` Dan Williams
2023-06-12 20:39   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 12/26] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-10  2:18   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 13/26] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-10  2:23   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 14/26] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-07 23:01   ` Concept of LD-ID in QEMU Shesha Bhushan Sreenivasamurthy
2023-06-08 10:31     ` Jonathan Cameron
2023-06-08 10:36       ` Jonathan Cameron
2023-06-08 10:36         ` Jonathan Cameron via
2023-06-08 23:38         ` [EXT] " Shesha Bhushan Sreenivasamurthy
2023-06-09 11:20           ` Jonathan Cameron
2023-06-09 11:20             ` Jonathan Cameron via
2023-06-10  2:29   ` [PATCH v5 14/26] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Dan Williams
2023-06-07 22:16 ` [PATCH v5 15/26] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-06-10  2:34   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 16/26] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-10  2:36   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 17/26] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-10  2:37   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 18/26] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-06-10  2:38   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 19/26] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-10  3:09   ` Dan Williams
2023-06-12 14:41     ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 20/26] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-10  3:11   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 21/26] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-10  3:12   ` Dan Williams
2023-06-12 21:12   ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 22/26] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-10  3:23   ` Dan Williams
2023-06-12 18:19     ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 23/26] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-12 20:29   ` Dan Williams
2023-06-13 15:28     ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 24/26] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-12 21:38   ` Dan Williams
2023-06-16 16:17     ` Terry Bowman
2023-06-16 16:28       ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 25/26] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-07 22:16   ` Terry Bowman
2023-06-08 22:54   ` kernel test robot
2023-06-08 22:54     ` kernel test robot
2023-06-12 22:49   ` Dan Williams
2023-06-12 22:49     ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 26/26] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-08 19:21   ` Bjorn Helgaas
2023-06-12 22:57   ` Dan Williams

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