From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mahesh Kumar Subject: Re: [PATCH] drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate Date: Thu, 1 Jun 2017 16:22:13 +0530 Message-ID: References: <20170601103413.7037-1-maarten.lankhorst@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0388789586==" Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id EB6486E322 for ; Thu, 1 Jun 2017 10:48:24 +0000 (UTC) In-Reply-To: <20170601103413.7037-1-maarten.lankhorst@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Maarten Lankhorst , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============0388789586== Content-Type: multipart/alternative; boundary="------------BD2DC30BA1228B72E5C747C7" This is a multi-part message in MIME format. --------------BD2DC30BA1228B72E5C747C7 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit hmm... didn't considered 2 pixels per clock. thanks. Reviewed-by: Mahesh Kumar On Thursday 01 June 2017 04:04 PM, Maarten Lankhorst wrote: > Seems that GLK has a dotclock that's twice the display clock. > skl_max_scale checks for IS_GEMINILAKE, so perform the same check here. > > While at it, change the DRM_ERROR to DEBUG_KMS. > > Fixes: 73b0ca8ec76d ("drm/i915/skl+: consider max supported plane pixel > rate while scaling") > Cc: Mahesh Kumar > Signed-off-by: Maarten Lankhorst > --- > drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 2042f6512e6e..88c8a3511e24 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4122,7 +4122,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, > struct drm_plane *plane; > const struct drm_plane_state *pstate; > struct intel_plane_state *intel_pstate; > - int crtc_clock, cdclk; > + int crtc_clock, dotclk; > uint32_t pipe_max_pixel_rate; > uint_fixed_16_16_t pipe_downscale; > uint_fixed_16_16_t max_downscale = u32_to_fixed_16_16(1); > @@ -4157,11 +4157,15 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, > pipe_downscale = mul_fixed16(pipe_downscale, max_downscale); > > crtc_clock = crtc_state->adjusted_mode.crtc_clock; > - cdclk = to_intel_atomic_state(state)->cdclk.logical.cdclk; > - pipe_max_pixel_rate = div_round_up_u32_fixed16(cdclk, pipe_downscale); > + dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk; > + > + if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev))) > + dotclk *= 2; > + > + pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale); > > if (pipe_max_pixel_rate < crtc_clock) { > - DRM_ERROR("Max supported pixel clock with scaling exceeded\n"); > + DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n"); > return -EINVAL; > } > --------------BD2DC30BA1228B72E5C747C7 Content-Type: text/html; charset=windows-1252 Content-Transfer-Encoding: 7bit

hmm... didn't considered 2 pixels per clock.

thanks.

Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com>

On Thursday 01 June 2017 04:04 PM, Maarten Lankhorst wrote:

Seems that GLK has a dotclock that's twice the display clock.
skl_max_scale checks for IS_GEMINILAKE, so perform the same check here.

While at it, change the DRM_ERROR to DEBUG_KMS.

Fixes: 73b0ca8ec76d ("drm/i915/skl+: consider max supported plane pixel
rate while scaling")
Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2042f6512e6e..88c8a3511e24 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4122,7 +4122,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	struct drm_plane *plane;
 	const struct drm_plane_state *pstate;
 	struct intel_plane_state *intel_pstate;
-	int crtc_clock, cdclk;
+	int crtc_clock, dotclk;
 	uint32_t pipe_max_pixel_rate;
 	uint_fixed_16_16_t pipe_downscale;
 	uint_fixed_16_16_t max_downscale = u32_to_fixed_16_16(1);
@@ -4157,11 +4157,15 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
 
 	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
-	cdclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
-	pipe_max_pixel_rate = div_round_up_u32_fixed16(cdclk, pipe_downscale);
+	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
+
+	if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
+		dotclk *= 2;
+
+	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
 
 	if (pipe_max_pixel_rate < crtc_clock) {
-		DRM_ERROR("Max supported pixel clock with scaling exceeded\n");
+		DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
 		return -EINVAL;
 	}

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