From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kever Yang Subject: Re: [PATCH v3 25/57] ram: rk3399: Avoid two channel ZQ Cal Start at the same time Date: Tue, 16 Jul 2019 21:12:42 +0800 Message-ID: References: <20190716115745.12585-1-jagan@amarulasolutions.com> <20190716115745.12585-26-jagan@amarulasolutions.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190716115745.12585-26-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Jagan Teki , Simon Glass , Philipp Tomsich , YouMin Chen , u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org, Manivannan Sadhasivam List-Id: linux-rockchip.vger.kernel.org Ck9uIDIwMTkvNy8xNiDkuIvljYg3OjU3LCBKYWdhbiBUZWtpIHdyb3RlOgo+IEl0IGlzIHBvc3Np YmxlIGluIGxwZGRyNCBkcmFtLCB3aGVyZSBib3RoIHRoZSBjaGFubmVscyB3b3VsZAo+IHN0YXJ0 IGF0IHNhbWUgdGltZSB3aXRoIFpRIENhbCBTdGFydC4gSWYgaXQgdXNlcyBaUSBDYWxsIHN0YXJ0 Cj4gdGhlbiBpdCB3aWxsIHVzZSBSWlEuCj4KPiBGb3IgZXhhbXBsZSBMUEREUjQgMzY2IER1YWwt RGllLCBRdWFkLUNoYW5uZWwgUGFja2FnZSwgUlpRIG1heWJlCj4gY29ubmVjdCB0byBib3RoIGNo YW5uZWwuIElmIFpRIENhbCBTdGFydCBhdCB0aGUgc2FtZSB0aW1lLAo+IGl0IHdpbGwgdXNlIHRo ZSBzYW1lIFJaUS4KPgo+IEl0IGlzIG5vdCBhIHByb2JsZW0gb2YgdXNpbmcgUlpRIGluIGJvdGgg dGhlIGNoYW5uZWxzLCBidXQgY2FuIG5vdAo+IHVzZSBhdCB0aGUgc2FtZSB0aW1lLgo+Cj4gU28s IHRvIGF2b2lkIHRoaXMsIHdlIGhhdmUgYW4gb3B0aW9uIG9mIGRyYW0gdElOSVQzIHZhbHVlIGZv cgo+IGluY3JlYXNpbmcgdGhlIGZyZXF1ZW5jeSBmb3IgY2hhbm5lbCAxLgo+Cj4gVGhpcyBwYXRj aCBpbmNyZWFzZSB0aGUgYXZhaWxhYmxlIHRJTklUMyB3aXRoIGV4aXN0aW5nIHJ1bm5pbmcKPiBk cmFtIGZyZXF1ZW5jeS4KPgo+IFNpZ25lZC1vZmYtYnk6IEphZ2FuIFRla2kgPGphZ2FuQGFtYXJ1 bGFzb2x1dGlvbnMuY29tPgo+IFNpZ25lZC1vZmYtYnk6IFlvdU1pbiBDaGVuIDxjeW1Acm9jay1j aGlwcy5jb20+CgpSZXZpZXdlZC1ieTogS2V2ZXIgWWFuZyA8S2V2ZXIueWFuZ0Byb2NrLWNoaXBz LmNvbT4KClRoYW5rcywKIMKgLSBLZXZlcgo+IC0tLQo+ICAgZHJpdmVycy9yYW0vcm9ja2NoaXAv c2RyYW1fcmszMzk5LmMgfCAxNCArKysrKysrKysrKysrKwo+ICAgMSBmaWxlIGNoYW5nZWQsIDE0 IGluc2VydGlvbnMoKykKPgo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3JhbS9yb2NrY2hpcC9zZHJh bV9yazMzOTkuYyBiL2RyaXZlcnMvcmFtL3JvY2tjaGlwL3NkcmFtX3JrMzM5OS5jCj4gaW5kZXgg MDIzODM4YTMwMS4uYmViNGY2ZGU1NCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL3JhbS9yb2NrY2hp cC9zZHJhbV9yazMzOTkuYwo+ICsrKyBiL2RyaXZlcnMvcmFtL3JvY2tjaGlwL3NkcmFtX3JrMzM5 OS5jCj4gQEAgLTU1MCw2ICs1NTAsMjAgQEAgc3RhdGljIGludCBwY3RsX2NmZyhzdHJ1Y3QgZHJh bV9pbmZvICpkcmFtLCBjb25zdCBzdHJ1Y3QgY2hhbl9pbmZvICpjaGFuLAo+ICAgCQkgICAgc2l6 ZW9mKHN0cnVjdCByazMzOTlfZGRyX3BjdGxfcmVncykgLSA0KTsKPiAgIAl3cml0ZWwocGFyYW1z X2N0bFswXSwgJmRlbmFsaV9jdGxbMF0pOwo+ICAgCj4gKwkvKgo+ICsJICogdHdvIGNoYW5uZWwg aW5pdCBhdCB0aGUgc2FtZSB0aW1lLCB0aGVuIFpRIENhbCBTdGFydAo+ICsJICogYXQgdGhlIHNh bWUgdGltZSwgaXQgd2lsbCB1c2UgdGhlIHNhbWUgUlpRLCBidXQgY2Fubm90Cj4gKwkgKiBzdGFy dCBhdCB0aGUgc2FtZSB0aW1lLgo+ICsJICoKPiArCSAqIFNvLCBpbmNyZWFzZSB0SU5JVDMgZm9y IGNoYW5uZWwgMSwgd2lsbCBhdm9pZCB0d28KPiArCSAqIGNoYW5uZWwgWlEgQ2FsIFN0YXJ0IGF0 IHRoZSBzYW1lIHRpbWUKPiArCSAqLwo+ICsJaWYgKHBhcmFtcy0+YmFzZS5kcmFtdHlwZSA9PSBM UEREUjQgJiYgY2hhbm5lbCA9PSAxKSB7Cj4gKwkJdG1wID0gKChwYXJhbXMtPmJhc2UuZGRyX2Zy ZXEgKiBNSHogKyA5OTkpIC8gMTAwMCk7Cj4gKwkJdG1wMSA9IHJlYWRsKCZkZW5hbGlfY3RsWzE0 XSk7Cj4gKwkJd3JpdGVsKHRtcCArIHRtcDEsICZkZW5hbGlfY3RsWzE0XSk7Cj4gKwl9Cj4gKwo+ ICAgCWNvcHlfdG9fcmVnKGRlbmFsaV9waSwgJnBhcmFtcy0+cGlfcmVncy5kZW5hbGlfcGlbMF0s Cj4gICAJCSAgICBzaXplb2Yoc3RydWN0IHJrMzM5OV9kZHJfcGlfcmVncykpOwo+ICAgCgoKCl9f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkxpbnV4LXJvY2tj aGlwIG1haWxpbmcgbGlzdApMaW51eC1yb2NrY2hpcEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6 Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcm9ja2NoaXAK From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kever Yang Date: Tue, 16 Jul 2019 21:12:42 +0800 Subject: [U-Boot] [PATCH v3 25/57] ram: rk3399: Avoid two channel ZQ Cal Start at the same time In-Reply-To: <20190716115745.12585-26-jagan@amarulasolutions.com> References: <20190716115745.12585-1-jagan@amarulasolutions.com> <20190716115745.12585-26-jagan@amarulasolutions.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On 2019/7/16 下午7:57, Jagan Teki wrote: > It is possible in lpddr4 dram, where both the channels would > start at same time with ZQ Cal Start. If it uses ZQ Call start > then it will use RZQ. > > For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe > connect to both channel. If ZQ Cal Start at the same time, > it will use the same RZQ. > > It is not a problem of using RZQ in both the channels, but can not > use at the same time. > > So, to avoid this, we have an option of dram tINIT3 value for > increasing the frequency for channel 1. > > This patch increase the available tINIT3 with existing running > dram frequency. > > Signed-off-by: Jagan Teki > Signed-off-by: YouMin Chen Reviewed-by: Kever Yang Thanks,  - Kever > --- > drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c > index 023838a301..beb4f6de54 100644 > --- a/drivers/ram/rockchip/sdram_rk3399.c > +++ b/drivers/ram/rockchip/sdram_rk3399.c > @@ -550,6 +550,20 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, > sizeof(struct rk3399_ddr_pctl_regs) - 4); > writel(params_ctl[0], &denali_ctl[0]); > > + /* > + * two channel init at the same time, then ZQ Cal Start > + * at the same time, it will use the same RZQ, but cannot > + * start at the same time. > + * > + * So, increase tINIT3 for channel 1, will avoid two > + * channel ZQ Cal Start at the same time > + */ > + if (params->base.dramtype == LPDDR4 && channel == 1) { > + tmp = ((params->base.ddr_freq * MHz + 999) / 1000); > + tmp1 = readl(&denali_ctl[14]); > + writel(tmp + tmp1, &denali_ctl[14]); > + } > + > copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0], > sizeof(struct rk3399_ddr_pi_regs)); >