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envelope-from=calebs@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Caleb Schlossin On 6/17/26 4:50 AM, Saif Abrar wrote: > From: Saif Abrar > > IODA PCT table is implemented > without any functionality, being a debug table. > > Signed-off-by: Saif Abrar > Reviewed-by: Cédric Le Goater > Reviewed-by: Aditya Gupta > Reviewed-by: Jishnu Warrier > --- > v5: Updated IODA3 PCT table max size to 128 * 2 entries each. > v3: Updates for coding guidelines. > > > hw/pci-host/pnv_phb4.c | 7 +++++++ > include/hw/pci-host/pnv_phb4.h | 2 ++ > include/hw/pci-host/pnv_phb4_regs.h | 1 + > 3 files changed, 10 insertions(+) > > diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c > index e9d9323dba..91b2064113 100644 > --- a/hw/pci-host/pnv_phb4.c > +++ b/hw/pci-host/pnv_phb4.c > @@ -264,6 +264,11 @@ static uint64_t *pnv_phb4_ioda_access(PnvPHB4 *phb, > mask = phb->big_phb ? PNV_PHB4_MAX_MIST : (PNV_PHB4_MAX_MIST >> 1); > mask -= 1; > break; > + case IODA3_TBL_PCT: > + tptr = phb->ioda_PCT; > + mask = phb->big_phb ? PNV_PHB4_MAX_PCT : (PNV_PHB4_MAX_PCT >> 1); > + mask -= 1; > + break; > case IODA3_TBL_RCAM: > mask = phb->big_phb ? 127 : 63; > break; > @@ -362,6 +367,8 @@ static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t val) > /* Handle side effects */ > switch (table) { > case IODA3_TBL_LIST: > + case IODA3_TBL_PCT: > + /* No action for debug tables */ > break; > case IODA3_TBL_MIST: { > /* Special mask for MIST partial write */ > diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h > index bea0684724..b7e15b87d1 100644 > --- a/include/hw/pci-host/pnv_phb4.h > +++ b/include/hw/pci-host/pnv_phb4.h > @@ -65,6 +65,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_BUS) > #define PNV_PHB4_MAX_LSIs 8 > #define PNV_PHB4_MAX_INTs 4096 > #define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2) > +#define PNV_PHB4_MAX_PCT (128 * 2) > #define PNV_PHB4_MAX_MMIO_WINDOWS 32 > #define PNV_PHB4_MIN_MMIO_WINDOWS 16 > #define PNV_PHB4_NUM_REGS (0x3000 >> 3) > @@ -138,6 +139,7 @@ struct PnvPHB4 { > /* On-chip IODA tables */ > uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; > uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; > + uint64_t ioda_PCT[PNV_PHB4_MAX_PCT]; > uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs]; > uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs]; > uint64_t ioda_MDT[PNV_PHB4_MAX_PEs]; > diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h > index c1d5a83271..e30adff7b2 100644 > --- a/include/hw/pci-host/pnv_phb4_regs.h > +++ b/include/hw/pci-host/pnv_phb4_regs.h > @@ -486,6 +486,7 @@ > > #define IODA3_TBL_LIST 1 > #define IODA3_TBL_MIST 2 > +#define IODA3_TBL_PCT 3 > #define IODA3_TBL_RCAM 5 > #define IODA3_TBL_MRT 6 > #define IODA3_TBL_PESTA 7