From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45F1FFF5137 for ; Tue, 7 Apr 2026 19:30:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wABVz-0007bq-0H; Tue, 07 Apr 2026 14:51:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wABTe-0002LR-Fq; Tue, 07 Apr 2026 14:48:43 -0400 Received: from out30-130.freemail.mail.aliyun.com ([115.124.30.130]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wA5JM-0006Qe-BV; Tue, 07 Apr 2026 08:13:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1775563998; h=Content-Type:Message-ID:Date:MIME-Version:Subject:To:From; bh=Ubpy7oxA8mF91aQ5SYyTW31HR+wTIT6hL8nveIqBu2g=; b=PxY2MTlYiz++68jcS85Yy7aBKqYkNSd6UQrGofyXCkG6JnwgSGTBhi6w1mws8MUgBxowjlM9FOG7VoPXOVErgMHkEFKpf8gXamsffQ3PLJVQRisyOZsZGQNkBkzzsysr5MmD5Uofmpi+a3GviMQ8qZQrz3c+HGC1eVkkjapAl/s= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R401e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045133197; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0X0bh4In_1775563997; Received: from 30.166.64.152(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0X0bh4In_1775563997 cluster:ay36) by smtp.aliyun-inc.com; Tue, 07 Apr 2026 20:13:17 +0800 Content-Type: multipart/alternative; boundary="------------q0WZad0400yN686Sbso3QxAq" Message-ID: Date: Tue, 7 Apr 2026 20:13:17 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check To: alistair23@gmail.com, palmer@dabbelt.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, chao.liu.zevorn@gmail.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alistair Francis References: <20260407043614.372871-1-alistair.francis@wdc.com> <20260407043614.372871-6-alistair.francis@wdc.com> Content-Language: en-US From: LIU Zhiwei In-Reply-To: <20260407043614.372871-6-alistair.francis@wdc.com> Received-SPF: pass client-ip=115.124.30.130; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-130.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This is a multi-part message in MIME format. --------------q0WZad0400yN686Sbso3QxAq Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Alistair, On 4/7/26 12:36 PM, alistair23@gmail.com wrote: > From: Alistair Francis > > The RISC-V spec states that > > """ > For a given supported fractional LMUL setting, implementations > must support SEW settings between SEWMIN and LMUL * ELEN, inclusive. > """ I think the meaning  of "must support"  in specification is "must at least support" instead of "must only support". Sail or Spike have the same check as this patch to prevent user program can run on them, but can't run on RTLs, as RTLs implementation may support SEW besides the SEWMIN and LMUL * ELEN range. We can refer to discussion here: https://github.com/riscv-software-src/riscv-isa-sim/pull/620 In my opinion, we had better add a option such as "frac_sew_check" to make user set right value for their RTL implementation. Otherwise, Reviewed-by: LIU Zhiwei Thanks, Zhiwei > We were previously checking VLEN, instead of ELEN, so let's update to > check ELEN instead of VLEN for fractional scaling. > > Resolves:https://gitlab.com/qemu-project/qemu/-/work_items/3196 > Signed-off-by: Alistair Francis > --- > target/riscv/vector_helper.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 83dd26314d..b4fc791eb7 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > target_ulong reserved = s2 & > MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, > xlen - 1 - R_VTYPE_RESERVED_SHIFT); > - uint16_t vlen = cpu->cfg.vlenb << 3; > int8_t lmul; > > if (vlmul & 4) { > /* > * Fractional LMUL, check: > * > - * VLEN * LMUL >= SEW > - * VLEN >> (8 - lmul) >= sew > - * (vlenb << 3) >> (8 - lmul) >= sew > + * ELEN * LMUL >= SEW > + * ELEN >> (8 - vlmul) >= sew > */ > - if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) { > + if (vlmul == 4 || > + (cpu->cfg.elen >> (8 - vlmul)) < sew) { > vill = true; > } > } --------------q0WZad0400yN686Sbso3QxAq Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit

Hi Alistair,

On 4/7/26 12:36 PM, alistair23@gmail.com wrote:
From: Alistair Francis <alistair.francis@wdc.com>

The RISC-V spec states that

"""
For a given supported fractional LMUL setting, implementations
must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.
"""

I think the meaning  of "must support"  in specification is "must at least support" instead of "must only support".

Sail or Spike have the same check as this patch to prevent user program can run on them, but
can't run on RTLs, as RTLs implementation may support SEW besides the  SEWMIN and LMUL * ELEN range.

We can refer to discussion here: https://github.com/riscv-software-src/riscv-isa-sim/pull/620

In my opinion, we had better add a option such as "frac_sew_check" to make user set right value for their RTL implementation.

Otherwise,
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Thanks,
Zhiwei

We were previously checking VLEN, instead of ELEN, so let's update to
check ELEN instead of VLEN for fractional scaling.

Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 83dd26314d..b4fc791eb7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     target_ulong reserved = s2 &
                             MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
                                             xlen - 1 - R_VTYPE_RESERVED_SHIFT);
-    uint16_t vlen = cpu->cfg.vlenb << 3;
     int8_t lmul;
 
     if (vlmul & 4) {
         /*
          * Fractional LMUL, check:
          *
-         * VLEN * LMUL >= SEW
-         * VLEN >> (8 - lmul) >= sew
-         * (vlenb << 3) >> (8 - lmul) >= sew
+         * ELEN * LMUL >= SEW
+         * ELEN >> (8 - vlmul) >= sew
          */
-        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
+        if (vlmul == 4 ||
+            (cpu->cfg.elen >> (8 - vlmul)) < sew) {
             vill = true;
         }
     }
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