From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A34C2C433EF for ; Sat, 25 Jun 2022 20:29:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233385AbiFYU3O (ORCPT ); Sat, 25 Jun 2022 16:29:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233285AbiFYU3M (ORCPT ); Sat, 25 Jun 2022 16:29:12 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11057DF21 for ; Sat, 25 Jun 2022 13:29:11 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id z7so7834023edm.13 for ; Sat, 25 Jun 2022 13:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=CyZdIB+a3zmI9o7okjV52QU2Tq6j8r50F7h1g1/ZmqM=; b=jh1P9SHTYiAY6bJeR6u5NXLil88CtmmVqCbzHotLRzOL2Uckkj8zWG4OGOELTd5s60 yyymcNJwXxFkpHnuqFpuqtjPJL7L8GVR6j1Yv+mxzhTqDuUWsXXe4Xq73f9dU6gJsT2M 9RC5dc6PF4Tfjrg64GyzSY2T3uIe9dS97Ybx6dQbikZ2qEUz2mgkL6UYSL1lZcVn1bVU NXpkl29vfd+iHN4xvmv0MnSxr/ln8wSE1K46AKqhsv2Lhu+XDwHNJ6WRqssjIlzBUaAf b6wVTAGq38CTBfNUF6dGDhRdnjWD4ebbw0MOTLuHr/bfGtYMKiCegkxvdAipfPMbeESd Lm9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=CyZdIB+a3zmI9o7okjV52QU2Tq6j8r50F7h1g1/ZmqM=; b=ztz9hR3mtk56WbGBL7ZaVVGDEuLjlQs5VERCKB7YsQzfzY7lxMdjTCN37kSLRybkQw /5AZfh129KWczL9JEv1GIhr0OxETXTM0hA1O8RI5wCBPyo/gGmDULZjYdI5T/7Z4K/12 L1jFhaOJVxsAZUXzMrFbPYLh8mRUolyMf9BWcu8MrRZV0ES5t4gd5WIy1sGj6xAqxdrS 1Rl7WO/nfLpfXGQrGZhhLTw5+83c5BHkycE1Vx+rm8v2G6GzfTLwYpF7G7HGNUcGdgKT PmPxPJECv2EbnZbk7oo37dWwh9DzxGKku3NhLsLf6ZrH7EX0l82Bf7kcRV7JMqNz/LxH Y5uA== X-Gm-Message-State: AJIora8YZmqtqt/g00TmWn7MIlJ5oi70rIP6eqtFgumhxpOIApchHsNj CGpdGd536dpIq80JqYSjXyqCcg== X-Google-Smtp-Source: AGRyM1v6ZQH0/qOeo1s9JIO2lBEu0I3AR8lap3IT4Akxx776t9v/QxwM3w6b6PhwZmfK4m5bsV8r/A== X-Received: by 2002:a05:6402:e0c:b0:435:25cd:6088 with SMTP id h12-20020a0564020e0c00b0043525cd6088mr6989495edh.60.1656188949672; Sat, 25 Jun 2022 13:29:09 -0700 (PDT) Received: from [192.168.0.239] (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id jw14-20020a170906e94e00b007263481a43fsm2644762ejb.81.2022.06.25.13.29.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Jun 2022 13:29:09 -0700 (PDT) Message-ID: Date: Sat, 25 Jun 2022 22:29:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v3 4/7] dt-bindings: clock: mediatek: Add clock driver bindings for MT6795 Content-Language: en-US To: AngeloGioacchino Del Regno , robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, y.oudjana@protonmail.com, jason-jh.lin@mediatek.com, ck.hu@mediatek.com, fparent@baylibre.com, rex-bc.chen@mediatek.com, tinghan.shen@mediatek.com, chun-jie.chen@mediatek.com, weiyi.lu@mediatek.com, ikjn@chromium.org, miles.chen@mediatek.com, sam.shih@mediatek.com, wenst@chromium.org, bgolaszewski@baylibre.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com References: <20220624093525.243077-1-angelogioacchino.delregno@collabora.com> <20220624093525.243077-5-angelogioacchino.delregno@collabora.com> From: Krzysztof Kozlowski In-Reply-To: <20220624093525.243077-5-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 24/06/2022 11:35, AngeloGioacchino Del Regno wrote: > Add the bindings for the clock drivers of the MediaTek Helio X10 > MT6795 SoC. > > Signed-off-by: AngeloGioacchino Del Regno > --- > .../bindings/clock/mediatek,mt6795-clock.yaml | 66 +++++++++++++++++ > .../clock/mediatek,mt6795-sys-clock.yaml | 74 +++++++++++++++++++ > 2 files changed, 140 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml > new file mode 100644 > index 000000000000..795fb18721c3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml > @@ -0,0 +1,66 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: MediaTek Functional Clock Controller for MT6795 > + > +maintainers: > + - AngeloGioacchino Del Regno > + - Chun-Jie Chen > + > +description: | > + The clock architecture in MediaTek like below > + PLLs --> > + dividers --> > + muxes > + --> > + clock gate > + > + The devices provide clock gate control in different IP blocks. > + > +properties: > + compatible: > + enum: > + - mediatek,mt6795-mfgcfg > + - mediatek,mt6795-vdecsys > + - mediatek,mt6795-vencsys > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + mfgcfg: clock-controller@13000000 { > + compatible = "mediatek,mt6795-mfgcfg"; > + reg = <0 0x13000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vdecsys: clock-controller@16000000 { > + compatible = "mediatek,mt6795-vdecsys"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencsys: clock-controller@18000000 { > + compatible = "mediatek,mt6795-vencsys"; > + reg = <0 0x18000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml > new file mode 100644 > index 000000000000..44b96af9ceaf > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: MediaTek System Clock Controller for MT6795 > + > +maintainers: > + - AngeloGioacchino Del Regno > + - Chun-Jie Chen > + > +description: > + The Mediatek system clock controller provides various clocks and system configuration Wrap according to Linux coding convention, so at 80. > + like reset and bus protection on MT6795. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt6795-apmixedsys > + - mediatek,mt6795-infracfg > + - mediatek,mt6795-pericfg > + - mediatek,mt6795-topckgen > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + topckgen: clock-controller@10000000 { > + compatible = "mediatek,mt6795-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: power-controller@10001000 { > + compatible = "mediatek,mt6795-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <1>; No need for four examples of the same. They differ only by compatible, so this is just unnecessary code... which as you can see does not pass the checks. This also has to be fixed. Maybe keep it as clock-controller? Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF340C43334 for ; Sat, 25 Jun 2022 20:30:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hHJV9yOWVj8/55BhVLtwnacZIrja3nAtV/C5BOyTGdE=; b=Wk/T7Rbc2IP+h3 FVQIvdOXMxLkQuHUNAmoxfhJ6PyePiKctfwuCsbWXd9u3vcOhBbmCeDSuUNbaYoF6GwgIebiIxzYr tqBRgPkRD7+qKs8dTYLerhC49QVgWyUGtF0H6s7DmW4D6Zy9J2JcWq0pMVqKAHlK3weNkYXC2vWf5 OOC6yAKGOas62diHrYsta2rWbcEvXo8vwDSypIt+RwHICso6vN0uR9H4jXOx4q53yvNKQ3Tt41idX rvnkjurg4DS0a6kayLu3oIYATnC/z8+j2JmSXCW1wAwX9bcs0Aplh2EVewrqpkOplSSxVlSvHdzst 2cSkbxQ1GWvAfEeC2d+Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5CP5-007h7c-TO; Sat, 25 Jun 2022 20:29:16 +0000 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5CP1-007h3X-Hy for linux-arm-kernel@lists.infradead.org; Sat, 25 Jun 2022 20:29:13 +0000 Received: by mail-ed1-x531.google.com with SMTP id z7so7834022edm.13 for ; Sat, 25 Jun 2022 13:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=CyZdIB+a3zmI9o7okjV52QU2Tq6j8r50F7h1g1/ZmqM=; b=jh1P9SHTYiAY6bJeR6u5NXLil88CtmmVqCbzHotLRzOL2Uckkj8zWG4OGOELTd5s60 yyymcNJwXxFkpHnuqFpuqtjPJL7L8GVR6j1Yv+mxzhTqDuUWsXXe4Xq73f9dU6gJsT2M 9RC5dc6PF4Tfjrg64GyzSY2T3uIe9dS97Ybx6dQbikZ2qEUz2mgkL6UYSL1lZcVn1bVU NXpkl29vfd+iHN4xvmv0MnSxr/ln8wSE1K46AKqhsv2Lhu+XDwHNJ6WRqssjIlzBUaAf b6wVTAGq38CTBfNUF6dGDhRdnjWD4ebbw0MOTLuHr/bfGtYMKiCegkxvdAipfPMbeESd Lm9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=CyZdIB+a3zmI9o7okjV52QU2Tq6j8r50F7h1g1/ZmqM=; b=OP8Lh5hgjBUSkMBgh2pzEwqmtMUt48twIk2ZexDC/9DkbVxua1nrXfQhB1cTwUiXW4 7UevsmeI8+ItZD86LMWOBp4kNJOQtozIuBghIQjH/Hvj324blwbeMCN0Pd1kYQfN2D1s dMLYLdvJIzp2Oz5ghlj8ZpmgA4+BYa0wxpMJ8jnngG7yWK3PC28Uqpz7qItWknyy4tWG sDq/ZwXu+Zbyxkkf5zhvejEJsj3nawJ48Miuq1B9klv8gbN1T54mkovgqEm0/BwmmWDm NiA2Ol3kMnwGWRkfdd6jAnzaqRnIcXvkfwFpRdirBveDuQ5fSBuR2dG0jsSI+XD2KIFd dPow== X-Gm-Message-State: AJIora/neXX9tmrw5hWXUlGC7IIQxNS4TLMuNRyDoDKgyDn0r4nAykqm ARae+ICzKSM+8taaE+fX5uXzbQ== X-Google-Smtp-Source: AGRyM1v6ZQH0/qOeo1s9JIO2lBEu0I3AR8lap3IT4Akxx776t9v/QxwM3w6b6PhwZmfK4m5bsV8r/A== X-Received: by 2002:a05:6402:e0c:b0:435:25cd:6088 with SMTP id h12-20020a0564020e0c00b0043525cd6088mr6989495edh.60.1656188949672; Sat, 25 Jun 2022 13:29:09 -0700 (PDT) Received: from [192.168.0.239] (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id jw14-20020a170906e94e00b007263481a43fsm2644762ejb.81.2022.06.25.13.29.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Jun 2022 13:29:09 -0700 (PDT) Message-ID: Date: Sat, 25 Jun 2022 22:29:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v3 4/7] dt-bindings: clock: mediatek: Add clock driver bindings for MT6795 Content-Language: en-US To: AngeloGioacchino Del Regno , robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, y.oudjana@protonmail.com, jason-jh.lin@mediatek.com, ck.hu@mediatek.com, fparent@baylibre.com, rex-bc.chen@mediatek.com, tinghan.shen@mediatek.com, chun-jie.chen@mediatek.com, weiyi.lu@mediatek.com, ikjn@chromium.org, miles.chen@mediatek.com, sam.shih@mediatek.com, wenst@chromium.org, bgolaszewski@baylibre.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com References: <20220624093525.243077-1-angelogioacchino.delregno@collabora.com> <20220624093525.243077-5-angelogioacchino.delregno@collabora.com> From: Krzysztof Kozlowski In-Reply-To: <20220624093525.243077-5-angelogioacchino.delregno@collabora.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220625_132911_684277_8D75B96D X-CRM114-Status: GOOD ( 18.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 24/06/2022 11:35, AngeloGioacchino Del Regno wrote: > Add the bindings for the clock drivers of the MediaTek Helio X10 > MT6795 SoC. > > Signed-off-by: AngeloGioacchino Del Regno > --- > .../bindings/clock/mediatek,mt6795-clock.yaml | 66 +++++++++++++++++ > .../clock/mediatek,mt6795-sys-clock.yaml | 74 +++++++++++++++++++ > 2 files changed, 140 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml > new file mode 100644 > index 000000000000..795fb18721c3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml > @@ -0,0 +1,66 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: MediaTek Functional Clock Controller for MT6795 > + > +maintainers: > + - AngeloGioacchino Del Regno > + - Chun-Jie Chen > + > +description: | > + The clock architecture in MediaTek like below > + PLLs --> > + dividers --> > + muxes > + --> > + clock gate > + > + The devices provide clock gate control in different IP blocks. > + > +properties: > + compatible: > + enum: > + - mediatek,mt6795-mfgcfg > + - mediatek,mt6795-vdecsys > + - mediatek,mt6795-vencsys > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + mfgcfg: clock-controller@13000000 { > + compatible = "mediatek,mt6795-mfgcfg"; > + reg = <0 0x13000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vdecsys: clock-controller@16000000 { > + compatible = "mediatek,mt6795-vdecsys"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencsys: clock-controller@18000000 { > + compatible = "mediatek,mt6795-vencsys"; > + reg = <0 0x18000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml > new file mode 100644 > index 000000000000..44b96af9ceaf > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: MediaTek System Clock Controller for MT6795 > + > +maintainers: > + - AngeloGioacchino Del Regno > + - Chun-Jie Chen > + > +description: > + The Mediatek system clock controller provides various clocks and system configuration Wrap according to Linux coding convention, so at 80. > + like reset and bus protection on MT6795. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt6795-apmixedsys > + - mediatek,mt6795-infracfg > + - mediatek,mt6795-pericfg > + - mediatek,mt6795-topckgen > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + topckgen: clock-controller@10000000 { > + compatible = "mediatek,mt6795-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: power-controller@10001000 { > + compatible = "mediatek,mt6795-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <1>; No need for four examples of the same. They differ only by compatible, so this is just unnecessary code... which as you can see does not pass the checks. This also has to be fixed. Maybe keep it as clock-controller? Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel