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From: William Roche <william.roche@oracle.com>
To: Borislav Petkov <bp@alien8.de>
Cc: yazen.ghannam@amd.com, tony.luck@intel.com, tglx@kernel.org,
	mingo@redhat.com, dave.hansen@linux.intel.com, x86@kernel.org,
	hpa@zytor.com, linux-edac@vger.kernel.org,
	linux-kernel@vger.kernel.org, John.Allen@amd.com,
	jane.chu@oracle.com
Subject: Re: [PATCH v2 1/1] x86/mce/amd: Fix VM crash during deferred error handling
Date: Mon, 16 Mar 2026 16:27:32 +0100	[thread overview]
Message-ID: <cedfbaf1-e2f1-4aa1-8825-d5faeeb09dbe@oracle.com> (raw)
In-Reply-To: <20260313201027.GHabRvM1wcctKe2Kut@fat_crate.local>

On 3/13/26 21:10, Borislav Petkov wrote:
> On Thu, Mar 12, 2026 at 11:44:04PM +0100, William Roche wrote:
>> Yazen, could you also please tell us if an existing non-SMCA AMD hardware
>> could crash on updating an SMCA register ?
> 
> So, the situation is this: if software needs to access a MCA_DESTATUS MSR
> - which is part of AMD's MCA extensions - then software needs to check the
>   smca bit.
> 
> So your patch is correct. The justification about it is not.
> 
> It should talk about how software should touch that MSR *only* *after* having
> checked mce_flags.smca.
> 

Ok, I understand your point.

> Because, it doesn't matter what KVM does or whoever - we all adhere to the hw
> spec.
> 
> Because technically speaking, this code should blow up on non-SMCA machines
> too because they do support deferred errors (Bulldozer for example) but they
> will #GP on access to the MCA_DESTATUS MSRs as those are reserved there.

This is a little more complicated as Yazen raised the situation in his 
answer. But I agree that SMCA specific registers are reserved and should 
not be accessed without checking that it is allowed to do so, first.

> 
> So please rewrite your commit message to state that. And then you can talk
> about what the real-life situation is which caught this.
> 

Sure, I'm going to submit a new version of this patch using this new 
commit message:

  x86/mce/amd: Guard SMCA DESTAT access on non-SMCA machines

  Access to SMCA specific registers like MCA_DESTAT should only be done
  after having checked the smca bit. Avoiding a non-SMCA machine (like
  AMD QEMU/KVM VMs) crash during deferred error handling.

  Fixes: 7cb735d7c0cb ("x86/mce: Unify AMD DFR handler with MCA Polling")
  Signed-off-by: William Roche <william.roche@oracle.com>
  Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
  Cc: stable@vger.kernel.org


> As to your use case - thanks for explaining it. If this is something which
> people run, then it would be wonderful if we had a simple test script in the
> kernel which verifies new changes don't break it and so that we can run it
> periodically as part of testing.

That would be great !
If there is a framework to create simple test script running the built 
kernel into a VM, I'd be happy to know about it and create the test we 
are talking about -- as a separate fix proposal.

Thanks again for your feedback,
William.

  reply	other threads:[~2026-03-16 15:28 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-18 16:30 [PATCH v2 0/1] AMD VM crashing on deferred memory error injection “William Roche
2026-02-18 16:30 ` [PATCH v2 1/1] x86/mce/amd: Fix VM crash during deferred error handling “William Roche
2026-03-12 14:42   ` Borislav Petkov
2026-03-12 15:11     ` William Roche
2026-03-12 16:04       ` Borislav Petkov
2026-03-12 22:44         ` William Roche
2026-03-13 20:10           ` Borislav Petkov
2026-03-16 15:27             ` William Roche [this message]
2026-03-13 20:26           ` Yazen Ghannam
2026-03-16 15:26             ` William Roche
2026-03-19 14:25               ` Yazen Ghannam
2026-03-12 14:23 ` [PATCH v2 0/1] AMD VM crashing on deferred memory error injection William Roche

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