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Thu, 22 Jun 2023 08:00:11 +0000 (GMT) Message-ID: Date: Thu, 22 Jun 2023 13:30:10 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH] target/ppc: Fix sc instruction handling of LEV field Content-Language: en-US To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Daniel Henrique Barboza References: <20230621110938.239066-1-npiggin@gmail.com> From: Harsh Prateek Bora In-Reply-To: <20230621110938.239066-1-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: JiJjaaOTmGM9p_yQHgIIhgue1ZuxXdGL X-Proofpoint-ORIG-GUID: zCWpQYLbTHhwtp59fpwfXoCKLwej9kru X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-22_04,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 clxscore=1015 mlxlogscore=795 spamscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306220062 Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.093, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/21/23 16:39, Nicholas Piggin wrote: > The top bits of the LEV field of the sc instruction are to be treated as > as a reserved field rather than a reserved value, meaning LEV is > effectively the bottom bit. LEV=0xF should be treated as LEV=1 and be > a hypercall, for example. > > This changes the instruction execution to just set lev from the low bit > of the field. Processors which don't support the LEV field will continue > to ignore it. > > ISA v3.1 defines LEV to be 2 bits, in order to add the 'sc 2' ultracall > instruction. TCG does not support Ultravisor, so don't worry about > that bit. > > Suggested-by: "Harsh Prateek Bora" > Signed-off-by: Nicholas Piggin > --- > This should probably go ahead of the ISA 3.1 LEV in SRR1 patch. I > don't think they need to be backported to stable though, have not > caused any real problems. > > Thanks to Harsh for spotting it. > > Thanks, > Nick > > target/ppc/translate.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 15a00bd4fa..3c62f9188a 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -4424,7 +4424,12 @@ static void gen_sc(DisasContext *ctx) > { > uint32_t lev; > > - lev = (ctx->opcode >> 5) & 0x7F; > + /* > + * LEV is a 7-bit field, but the top 6 bits are treated as a reserved > + * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is > + * for Ultravisor which TCG does not support, so just ignore the top 6. > + */ > + lev = (ctx->opcode >> 5) & 0x1; should this change be applied to gen_scv() defined next to it as well ? Otherwise, Reviewed-by: Harsh Prateek Bora > gen_exception_err(ctx, POWERPC_SYSCALL, lev); > } >