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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V Content-Language: en-US To: Nathan Egge , Palmer Dabbelt , Alistair Francis , Bin Meng Cc: Weiwei Li , Liu Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org References: <20230803131424.40744-1-negge@xiph.org> From: Daniel Henrique Barboza In-Reply-To: <20230803131424.40744-1-negge@xiph.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.091, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 8/3/23 10:14, Nathan Egge wrote: > From: "Nathan Egge" > > Set V bit for hwcap if misa is set. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793 > Signed-off-by: Nathan Egge > --- Tested with the example program described in the bug: =========== #include #include #define ISA_V_HWCAP (1 << ('v' - 'a')) void main() { unsigned long hw_cap = getauxval(AT_HWCAP); printf("RVV %s\n", hw_cap & ISA_V_HWCAP ? "detected" : "not found"); } =========== $ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,v=true,vlen=128 -B 0x100000 ./a.out RVV detected $ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,vlen=128 -B 0x100000 ./a.out RVV not found Reviewed-by: Daniel Henrique Barboza Tested-by: Daniel Henrique Barboza Looks like 8.1 material to me. Thanks, Daniel > linux-user/elfload.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 861ec07abc..a299ba7300 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void) > #define MISA_BIT(EXT) (1 << (EXT - 'A')) > RISCVCPU *cpu = RISCV_CPU(thread_cpu); > uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') > - | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); > + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C') > + | MISA_BIT('V'); > > return cpu->env.misa_ext & mask; > #undef MISA_BIT