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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c12024deb90sm796925666b.18.2026.06.29.07.33.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Jun 2026 07:33:48 -0700 (PDT) Message-ID: Date: Mon, 29 Jun 2026 16:33:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] arm: handle demuxed ID registers Content-Language: en-US To: Sebastian Ott , Peter Maydell , Jonathan Cameron , Alireza Sanaee , Richard Henderson , Cornelia Huck Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20260622135627.40573-1-sebott@redhat.com> <20260622135627.40573-2-sebott@redhat.com> From: Eric Auger In-Reply-To: <20260622135627.40573-2-sebott@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eauger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/22/26 3:56 PM, Sebastian Ott wrote: > From: Cornelia Huck > > For some registers, we do not have a single ID register, but actually > an array of values (e.g. CCSIDR_EL1, where the actual value is > determined by whatever CSSELR_EL1 points to.) If we want to avoid > using a different way to handle registers like that for every > instance, we should provide some kind of infrastructure. Therefore, > add accessors {GET,SET}_IDREG_DEMUX that are similar to the accessors > we already use for regular ID registers. > > Tested-by: Alireza Sanaee > Signed-off-by: Cornelia Huck > Signed-off-by: Sebastian Ott With actual implementation Suggested-by: Richard Henderson Reviewed-by: Eric Auger Eric > --- > target/arm/cpu-sysregs.h | 9 +++++++++ > target/arm/cpu.h | 12 ++++++++++++ > target/arm/cpu64.c | 8 ++++++++ > 3 files changed, 29 insertions(+) > > diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h > index 7877a3b06a..a4b9621a7e 100644 > --- a/target/arm/cpu-sysregs.h > +++ b/target/arm/cpu-sysregs.h > @@ -20,20 +20,29 @@ > > #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX, > > +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ > + NAME##_IDX, \ > + NAME##_IDX_LAST = NAME##_IDX + NUM - 1, > + > typedef enum ARMIDRegisterIdx { > #include "cpu-sysregs.h.inc" > NUM_ID_IDX, > } ARMIDRegisterIdx; > > #undef DEF > +#undef DEF_MUX > #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ > SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2), > > +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ > + DEF(NAME, OP0, OP1, CRN, CRM, OP2) > + > typedef enum ARMSysRegs { > #include "cpu-sysregs.h.inc" > } ARMSysRegs; > > #undef DEF > +#undef DEF_MUX > > extern const uint32_t id_register_sysreg[NUM_ID_IDX]; > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 31a5567c95..fe0046b02e 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -919,6 +919,18 @@ typedef struct { > i_->idregs[REG ## _EL1_IDX]; \ > }) > > +#define SET_IDREG_DEMUX(ISAR, REG, INDEX, VALUE) \ > + ({ \ > + ARMISARegisters *i_ = (ISAR); \ > + i_->idregs[REG ## _IDX + INDEX] = VALUE; \ > + }) > + > +#define GET_IDREG_DEMUX(ISAR, REG, INDEX) \ > + ({ \ > + ARMISARegisters *i_ = (ISAR); \ > + i_->idregs[REG ## _IDX + INDEX]; \ > + }) > + > /** > * ARMCPU: > * @env: #CPUARMState > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 2816735577..48a0421674 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -42,14 +42,21 @@ > #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ > [NAME##_IDX] = SYS_##NAME, > > +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ > + DEF(NAME, OP0, OP1, CRN, CRM, OP2) > + > const uint32_t id_register_sysreg[NUM_ID_IDX] = { > #include "cpu-sysregs.h.inc" > }; > > #undef DEF > +#undef DEF_MUX > #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ > case SYS_##NAME: return NAME##_IDX; > > +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ > + DEF(NAME, OP0, OP1, CRN, CRM, OP2) > + > int get_sysreg_idx(ARMSysRegs sysreg) > { > switch (sysreg) { > @@ -59,6 +66,7 @@ int get_sysreg_idx(ARMSysRegs sysreg) > } > > #undef DEF > +#undef DEF_MUX > > void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) > {