From: "Zhijian Li (Fujitsu)" <lizhijian@fujitsu.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
Dave Jiang <dave.jiang@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] cxl/acpi: Verify CHBS length for CXL2.0
Date: Mon, 7 Apr 2025 01:52:40 +0000 [thread overview]
Message-ID: <cfd77ff7-8dae-4994-affb-d2cdaaace33a@fujitsu.com> (raw)
In-Reply-To: <20250404145331.00001559@huawei.com>
On 04/04/2025 21:53, Jonathan Cameron wrote:
>> While the immediate impact might be limited to edge cases (e.g., incorrect QEMU configurations),
>> upstreaming this aligns the kernel with spec-mandated checks and improves
>> robustness for future use cases.
>>
>> [1]https://cdrdv2-public.intel.com/643805/643805_CXL_Memory_Device_SW_Guide_Rev1_1.pdf
> Just to check - are we talking hacked QEMU or some configuration of QEMU that
> can generate the wrong length?
A hacked QEMU.
>
> Jonathan
next prev parent reply other threads:[~2025-04-07 1:52 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-26 7:44 [PATCH] cxl/acpi: Verify CHBS length for CXL2.0 Li Zhijian
2025-03-27 3:44 ` Ira Weiny
2025-03-27 7:44 ` Zhijian Li (Fujitsu)
2025-03-27 13:36 ` Dan Williams
2025-03-28 4:15 ` Zhijian Li (Fujitsu)
2025-04-04 13:53 ` Jonathan Cameron
2025-04-07 1:52 ` Zhijian Li (Fujitsu) [this message]
2025-04-04 22:19 ` Dan Williams
2025-04-07 2:30 ` Zhijian Li (Fujitsu)
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