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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e642d1b70sm19942565e9.2.2026.05.08.05.08.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 May 2026 05:08:24 -0700 (PDT) Message-ID: Date: Fri, 8 May 2026 14:08:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 7/7] qemu-options.hx: Support "auto" for accel SMMUv3 properties To: Nathan Chen , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Marcel Apfelbaum , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Yanan Wang , Zhao Liu , Shameer Kolothum , Matt Ochs , Nicolin Chen References: <20260422204335.23116-1-nathanc@nvidia.com> <20260422204335.23116-8-nathanc@nvidia.com> From: Eric Auger In-Reply-To: <20260422204335.23116-8-nathanc@nvidia.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: sNyrp3z0Y5HOEsGvA7Ku_n074-jqk6Om38VIkIrxTQk_1778242106 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.44, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi Nathan, On 4/22/26 10:43 PM, Nathan Chen wrote: > Update documentation now that "auto" is supported for accelerated SMMUv3 > properties. > > Signed-off-by: Nathan Chen > --- > qemu-options.hx | 33 +++++++++++++++++++++++---------- > 1 file changed, 23 insertions(+), 10 deletions(-) > > diff --git a/qemu-options.hx b/qemu-options.hx > index 21972f8326..2c6ba16a26 100644 > --- a/qemu-options.hx > +++ b/qemu-options.hx > @@ -1291,30 +1291,43 @@ SRST > Enabling accel configures the host SMMUv3 in nested mode to support > vfio-pci passthrough. > > - The following options are available when accel=on. > - Note: 'auto' mode is not currently supported. > - > - ``ril=on|off`` (default: on) > + The following options will be set to auto by default if not manually > + set. When accel=on and these properties are set to auto, the value is > + derived from the host SMMUv3 capabilities via IOMMU_GET_HW_INFO. With > + accel=on, this requires at least one cold-plugged vfio-pci device; if > + none is present at machine init, QEMU will abort. > + > + If accel=off and these property values are set to auto, the values will > + not be derived from the host SMMUv3 capabilities. Instead, they will > + resolve to the defaults described below, and a cold-plugged vfio-pci > + device is not required. I would simply say: If accel=off auto values resolve to the non accel default given below. > + > + ``ril=on|off`` (default: auto) ril=on|off|auto (default: auto)           ------- I would rewrite it into: Support for Range Invalidation, which allows the SMMUv3 driver to invalidate TLB entries for a range of IOVAs at once instead of issuing separate commands to invalidate each page. - with accel=on auto means the value is automatically derived from the host SMMU if explicitly set to 'on', the host must also support it. - with accel=off auto is resolved into 'on' If we have this explanation here in object_class_property_set_description() just explain the basic semantic and list the valid values and default value. No use to rexplain the auto mode semantic. > Support for Range Invalidation, which allows the SMMUv3 driver to > invalidate TLB entries for a range of IOVAs at once instead of issuing > separate commands to invalidate each page. Must match with host SMMUv3 > - Range Invalidation support. > + Range Invalidation support. If accel=off and ril is set to auto, this > + property value will resolve to on. Same for the others ... Thanks Eric > > - ``ats=on|off`` (default: off) > + ``ats=on|off`` (default: auto) > Support for Address Translation Services, which enables PCIe devices to > cache address translations in their local TLB and reduce latency. Host > SMMUv3 must support ATS in order to enable this feature for the vIOMMU. > + If accel=off and ats is set to auto, the property value will resolve to > + off. > > - ``oas=val`` (supported values are 44 and 48. default: 44) > + ``oas=val`` (supported values are 44 and 48. default: auto) > Sets the Output Address Size in bits. The value set here must be less > than or equal to the host SMMUv3's supported OAS, so that the > intermediate physical addresses (IPA) consumed by host SMMU for stage-2 > - translation do not exceed the host's max supported IPA size. > + translation do not exceed the host's max supported IPA size. If > + accel=off and oas is set to auto, the property value will resolve to 44. > > - ``ssidsize=val`` (val between 0 and 20. default: 0) > + ``ssidsize=val`` (val between 0 and 20. default: auto) > Sets the Substream ID size in bits. When set to a non-zero value, > PASID capability is advertised to the vIOMMU and accelerated use cases > - such as Shared Virtual Addressing (SVA) are supported. > + such as Shared Virtual Addressing (SVA) are supported. If accel=off > + and ssidsize is set to auto, the property value will resolve to 0. > > ``-device amd-iommu[,option=...]`` > Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU).