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Mon, 28 Apr 2025 04:34:35 -0700 (PDT) Received: from [192.168.68.110] ([152.234.125.33]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db51026dfsm80351235ad.170.2025.04.28.04.34.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Apr 2025 04:34:35 -0700 (PDT) Message-ID: Date: Mon, 28 Apr 2025 08:34:31 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong To: Andrew Jones Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com References: <20250425160203.2774835-1-dbarboza@ventanamicro.com> <20250425160203.2774835-9-dbarboza@ventanamicro.com> <20250427-e13fa003b1bfad48e17bcee9@orel> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20250427-e13fa003b1bfad48e17bcee9@orel> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 4/27/25 2:59 AM, Andrew Jones wrote: > On Fri, Apr 25, 2025 at 01:02:02PM -0300, Daniel Henrique Barboza wrote: >> We want to support scounteren as a KVM CSR. The KVM UAPI defines every >> CSR size as target_ulong, and our env->scounteren is fixed at 32 bits. >> >> The other existing cases where the property size does not match the KVM >> reg size happens with uint64_t properties, like 'mstatus'. When running >> a 32 bit CPU we'll write a 32 bit 'sstatus' KVM reg into the 64 bit >> 'mstatus' field. As long as we're consistent, i.e. we're always >> reading/writing the same words, this is ok. >> >> For scounteren, a KVM guest running in a 64 bit CPU will end up writing >> a 64 bit reg in a 32 bit field. This will have all sort of funny side >> effects in the KVM guest that we would rather avoid. >> >> Increase scounteren to target_ulong to allow KVM to read/write the >> scounteren CSR without any surprises. >> >> Aside from bumping the version of the RISCVCPU vmstate no other >> behavioral changes are expected. >> >> Signed-off-by: Daniel Henrique Barboza >> --- >> target/riscv/cpu.h | 9 ++++++++- >> target/riscv/machine.c | 6 +++--- >> 2 files changed, 11 insertions(+), 4 deletions(-) >> >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index f5a60d0c52..66d4ddfcb4 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -400,7 +400,14 @@ struct CPUArchState { >> */ >> bool two_stage_indirect_lookup; >> >> - uint32_t scounteren; >> + /* >> + * scounteren is supposed to be an uint32_t, as the spec >> + * says. We're using a target_ulong instead because the >> + * scounteren KVM CSR is defined as target_ulong in >> + * kvm_riscv_csr, and we want to avoid having to deal >> + * with an ulong reg being read/written in an uint32_t. >> + */ >> + target_ulong scounteren; > > I'm having second thoughts about this. It seems like it should be > avoidable with the use of an intermediary buffer (which we already > have -- the uint64_t reg) and with tracking the size of the env state > by capturing the size with the new macro used to build the array. scounteren is an uint32_t field so I'm not sure why we need to track it. > Then, > > for reading: > 1. read the kvm reg into a buffer of the size kvm says it is > 2. only write the bytes we can store from the buffer into the env state, > using the size field to know how many that is > > for writing: > 1. put the env state into a buffer of the size kvm says the register is, > ensuring any upper unused bytes of the buffer are zero > 2. write the buffer to kvm So in short we would just read/write the lower 32 bits of scounteren, making it a 32 bit CSR as far as QEMU is concerned. Given that it is a 32 bit CSR in the RISC-V ISA too I guess it's safe for QEMU to do this assumption. Thanks, Daniel > > Thanks, > drew > >> uint32_t mcounteren; >> >> uint32_t scountinhibit; >> diff --git a/target/riscv/machine.c b/target/riscv/machine.c >> index df2d5bad8d..f3477e153b 100644 >> --- a/target/riscv/machine.c >> +++ b/target/riscv/machine.c >> @@ -401,8 +401,8 @@ static const VMStateDescription vmstate_ssp = { >> >> const VMStateDescription vmstate_riscv_cpu = { >> .name = "cpu", >> - .version_id = 10, >> - .minimum_version_id = 10, >> + .version_id = 11, >> + .minimum_version_id = 11, >> .post_load = riscv_cpu_post_load, >> .fields = (const VMStateField[]) { >> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), >> @@ -445,7 +445,7 @@ const VMStateDescription vmstate_riscv_cpu = { >> VMSTATE_UINTTL(env.mtval, RISCVCPU), >> VMSTATE_UINTTL(env.miselect, RISCVCPU), >> VMSTATE_UINTTL(env.siselect, RISCVCPU), >> - VMSTATE_UINT32(env.scounteren, RISCVCPU), >> + VMSTATE_UINTTL(env.scounteren, RISCVCPU), >> VMSTATE_UINT32(env.mcounteren, RISCVCPU), >> VMSTATE_UINT32(env.scountinhibit, RISCVCPU), >> VMSTATE_UINT32(env.mcountinhibit, RISCVCPU), >> -- >> 2.49.0 >>