From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Ross Subject: [PATCH 0/2] drm/i915: interlaced mode support (G35 VGA/SDVO) Date: Sun, 15 Jan 2012 01:52:00 +1100 Message-ID: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2055941008==" Return-path: Received: from fallbackmx09.syd.optusnet.com.au (fallbackmx09.syd.optusnet.com.au [211.29.132.242]) by gabe.freedesktop.org (Postfix) with ESMTP id F05F99E760 for ; Sat, 14 Jan 2012 06:52:04 -0800 (PST) Received: from mail08.syd.optusnet.com.au (mail08.syd.optusnet.com.au [211.29.132.189]) by fallbackmx09.syd.optusnet.com.au (8.13.1/8.13.1) with ESMTP id q0EEq3C7008807 for ; Sun, 15 Jan 2012 01:52:03 +1100 Received: from [127.0.1.1] (c114-76-133-225.sunsh2.vic.optusnet.com.au [114.76.133.225]) (authenticated sender peterross79) by mail08.syd.optusnet.com.au (8.13.1/8.13.1) with ESMTP id q0EEq04Q029564 for ; Sun, 15 Jan 2012 01:52:00 +1100 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============2055941008== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="X1bOJ3K7DJ5YkBrT" Content-Disposition: inline --X1bOJ3K7DJ5YkBrT Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable This patch set enables enables interlaced mode output on the VGA and SDVO connectors of the G35 chipset. History here: https://bugs.freedesktop.org/show_bug.cgi?id=3D11220 I have tested the changes on an ASUS P5E-VM-HDMI mainboard with VGA and HDMI CRTs attached. The G45 and SB documentation suggests that this will also work on those chipsets. (Wording of the vertical timing registers is near identical). Feedback welcome. Peter Ross (2): drm/i915: specify vertical timings in frame units for interlaced modes (gen4+) drm/i915: allow interlaced mode output on the SDVO connector drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ drivers/gpu/drm/i915/intel_sdvo.c | 2 +- 2 files changed, 9 insertions(+), 1 deletions(-) --=20 1.7.5.4 -- Peter (A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B) --X1bOJ3K7DJ5YkBrT Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iEYEARECAAYFAk8Rlo8ACgkQZ2B5xaxA3WvKLACeMm9tEF/qsY2jy3sr9JKkB+93 noEAn1smGgI6XXPlA5cLMAYPGHmg5T6U =w0vh -----END PGP SIGNATURE----- --X1bOJ3K7DJ5YkBrT-- --===============2055941008== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============2055941008==--