From: Alistair Francis <alistair.francis@xilinx.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, alindsay@codeaurora.org,
alistair.francis@xilinx.com, crosthwaitepeter@gmail.com,
cov@codeaurora.org, nathan@nathanrossi.com
Subject: [Qemu-devel] [PATCH v1 0/3] Extend the performance monitoring registers
Date: Wed, 3 Feb 2016 16:34:44 -0800 [thread overview]
Message-ID: <cover.1454545837.git.alistair.francis@xilinx.com> (raw)
This patch set is based on the patch sent by Christopher Covington and
written by Aaron Lindsay which was sent as an RFC (Implement remaining
PMU functionality).
It adds a few performance monitoring related registers.
Alistair Francis (3):
target-arm: Add the pmceid0 and pmceid1 registers
target-arm: Add Some of the performance monitor registers
target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers
target-arm/cpu-qom.h | 2 +
target-arm/cpu.c | 2 +
target-arm/cpu.h | 6 +++
target-arm/cpu64.c | 2 +
target-arm/helper.c | 109 +++++++++++++++++++++++++++++++++++++++++++++------
5 files changed, 110 insertions(+), 11 deletions(-)
--
2.5.0
next reply other threads:[~2016-02-04 0:37 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-04 0:34 Alistair Francis [this message]
2016-02-04 0:34 ` [Qemu-devel] [PATCH v1 1/3] target-arm: Add the pmceid0 and pmceid1 registers Alistair Francis
2016-02-05 13:08 ` Nathan Rossi
2016-02-04 0:34 ` [Qemu-devel] [PATCH v1 2/3] target-arm: Add Some of the performance monitor registers Alistair Francis
2016-02-05 13:08 ` Nathan Rossi
2016-02-04 0:34 ` [Qemu-devel] [PATCH v1 3/3] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers Alistair Francis
2016-02-05 13:09 ` Nathan Rossi
2016-02-04 13:39 ` [Qemu-devel] [PATCH v1 0/3] Extend the performance monitoring registers Aaron Lindsay
2016-02-04 18:52 ` Alistair Francis
2016-02-05 13:37 ` Aaron Lindsay
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