From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 07 Feb 2019 23:43:17 -0000 Received: from mga06.intel.com ([134.134.136.31]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1grtI9-0006JT-C1 for speck@linutronix.de; Fri, 08 Feb 2019 00:41:15 +0100 From: Andi Kleen Subject: [MODERATED] [PATCH v3 0/6] PERFv3 Date: Thu, 7 Feb 2019 15:41:02 -0800 Message-Id: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 To: speck@linutronix.de Cc: Andi Kleen List-ID: Walnut is an functional (not security) issue with TSX. The upcoming microcode updates on Skylake may corrupt perfmon counter 3 when RTM transactions are used. There is a new MSR that allows to force abort RTM, and free counter 3. The following patchkit adds the support to perf to avoid using counter 3, or disabling TSX when counter 3 is needed for perf. There are per perf event and global options to set the default. This patch sets the default to TSX enabled, but that could be easily changed. We can have a discussion on the trade offs of the default setting. I suspect it's a decision that should be made by Linus, as it may impact user programs either way. The trade offs for setting the option default are: Using 4 (or 8 with HT off) events in perf versus allowing RTM usage while perf is active. - Existing programs that use perf groups with 4 counters may not retrieve perfmon data anymore. Perf usages that use less than four (or 7 with HT off) counters are not impacted. Perf usages that don't use group will still work, but will see increase multiplexing. - TSX programs should not functionally break from forcing RTM to abort because they always need a valid fall back path. However they will see significantly lower performance if they rely on TSX for performance (all RTM transactions will run and only abort at the end), potentially slowing them down so much that it is equivalent to functional breakage. Patches are against tip/perf/core as of commit ca3bb3d027f69ac3ab1dafb32bde2f5a3a44439c (tip/perf/core) Author: Elena Reshetova -Andi v1: Initial post v2: Minor updates in code (see individual patches) Removed optimization to not change MSR for update. This caused missing MSR updates in some cases. Redid KVM code to always intercept MSR and pass correct flag to host perf. v3: Use Peter's scheduling patch, with some changes and cleanups. Dropped some obsolete patches. KVM now always forces the guest state and doesn't rely on the host state. Andi Kleen (6): x86/pmu/intel: Export number of counters in caps x86/pmu/intel: Handle TSX with counter 3 on Skylake x86/pmu/intel: Add perf event attribute to control RTM perf stat: Make all existing groups weak perf stat: Don't count EL for --transaction with three counters kvm: vmx: Support TSX_FORCE_ABORT in KVM guests arch/x86/events/core.c | 24 ++++++++ arch/x86/events/intel/core.c | 94 +++++++++++++++++++++++++++++- arch/x86/events/perf_event.h | 13 ++++- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 5 ++ arch/x86/kvm/cpuid.c | 3 +- arch/x86/kvm/pmu.c | 19 +++--- arch/x86/kvm/pmu.h | 6 +- arch/x86/kvm/pmu_amd.c | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 20 ++++++- tools/perf/builtin-stat.c | 38 ++++++++---- tools/perf/util/pmu.c | 10 ++++ tools/perf/util/pmu.h | 1 + 14 files changed, 211 insertions(+), 26 deletions(-) -- 2.17.2