From: Chao Liu <lc00631@tecorigin.com>
To: palmer@dabbelt.com, alistair23@gmail.com
Cc: zhiwei_liu@linux.alibaba.com, alistair.francis@wdc.com,
dbarboza@ventanamicro.com, liwei1518@gmail.com,
zhangtj@tecorigin.com, zqz00548@tecorigin.com,
lc00631@tecorigin.com, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Subject: [PATCH v2 0/1] fix the way riscv_plic_hart_config_string() gets the CPUState
Date: Wed, 16 Apr 2025 12:53:57 +0800 [thread overview]
Message-ID: <cover.1744776027.git.lc00631@tecorigin.com> (raw)
Hi, all:
I made the following changes in version 2 of the patch:
Regarding the plic initialization phase to get CPUState by traversing
qemu_get_cpu(), this is an early design flaw, a better approach would be to use
riscv's hartid for indexing via the interface cpu_by_arch_id().
PATCH v1:
https://lore.kernel.org/qemu-riscv/416e68f4-bf12-4218-ae2d-0246cc8ea8ec@linaro.org/T/#u
--
Regards,
Chao
Chao Liu (1):
hw/riscv: fix PLIC hart topology configuration string when not getting
CPUState correctly
hw/intc/sifive_plic.c | 2 +-
hw/riscv/boot.c | 4 ++--
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/sifive_u.c | 5 +++--
hw/riscv/virt.c | 2 +-
include/hw/riscv/boot.h | 2 +-
6 files changed, 9 insertions(+), 8 deletions(-)
--
2.48.1
next reply other threads:[~2025-04-16 4:58 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-16 4:53 Chao Liu [this message]
2025-04-16 4:53 ` [PATCH v2 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly Chao Liu
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