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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2025 03:43:17.9216 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23bc38cf-a444-435a-f03c-08dd7e2b2844 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7780 Uncore counters on AMD processors either roll over or saturate on overflow and the amd-uncore driver has no way of knowing if multiple overflows have occurred between two successive pmu->read() requests for an event. This makes the user-visible counter values inaccurate. Solve this by periodically initiating pmu->read() in order to keep prev_count up-to-date. The approach follows Intel's precedent in handling uncore counters. Previous versions can be found at: v1: https://lore.kernel.org/all/cover.1744184837.git.sandipan.das@amd.com/ Changes in v2: - Add a Fixes tag for the first patch. - Change the hrtimer mode for both the Intel and the AMD uncore drivers based on Peter's suggestion. - Fix an issue in the UMC workaround where prev_count is not zeroed out after a counter is reset. Sandipan Das (5): perf/x86/amd/uncore: Remove unused member from amd_uncore_ctx perf/x86/intel/uncore: Use HRTIMER_MODE_HARD for detecting overflows perf/x86/amd/uncore: Use hrtimer for handling overflows perf/x86/amd/uncore: Add parameter to configure hrtimer perf/x86/amd/uncore: Prevent UMC counters from saturating arch/x86/events/amd/uncore.c | 103 ++++++++++++++++++++++++++++++++- arch/x86/events/intel/uncore.c | 12 +--- 2 files changed, 103 insertions(+), 12 deletions(-) -- 2.43.0