From: Chao Liu <chao.liu@yeah.net>
To: paolo.savini@embecosm.com, ebiggers@kernel.org,
dbarboza@ventanamicro.com, palmer@dabbelt.com,
alistair.francis@wdc.com, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Chao Liu <chao.liu@yeah.net>
Subject: [PATCH v3 0/2] [RISCV/RVV] Generate strided vector loads/stores with tcg nodes.
Date: Sat, 16 Aug 2025 08:56:41 +0800 [thread overview]
Message-ID: <cover.1755305184.git.chao.liu@yeah.net> (raw)
Hi Paolo, Eric, Daniel,
patch v3 changes:
- Fix the get_log2 cunftion:
https://lore.kernel.org/qemu-riscv/cover.1755287531.git.chao.liu@yeah.net/T/#t
- Add test for vlsseg8e32 instruction.
- Rebase on top of the latest master.
patch v2 changes:
- Split the TCG node emulation of the complex strided load/store operation into
two separate functions to simplify the implementation:
https://lore.kernel.org/qemu-riscv/20250312155547.289642-1-paolo.savini@embecosm.com/
Best regards,
Chao
Chao Liu (2):
Generate strided vector loads/stores with tcg nodes.
tests/tcg/riscv64: Add test for vlsseg8e32 instruction
target/riscv/insn_trans/trans_rvv.c.inc | 326 ++++++++++++++++++----
tests/tcg/riscv64/Makefile.softmmu-target | 8 +-
tests/tcg/riscv64/test-vlsseg8e32.S | 107 +++++++
3 files changed, 389 insertions(+), 52 deletions(-)
create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S
--
2.50.1
next reply other threads:[~2025-08-16 0:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-16 0:56 Chao Liu [this message]
2025-08-16 0:56 ` [PATCH v3 1/2] Generate strided vector loads/stores with tcg nodes Chao Liu
2025-08-16 6:52 ` Richard Henderson
2025-08-16 8:39 ` Chao Liu
2025-08-16 0:56 ` [PATCH v3 2/2] tests/tcg/riscv64: Add test for vlsseg8e32 instruction Chao Liu
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