All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Naveen N Rao (AMD)" <naveen@kernel.org>
To: qemu-devel <qemu-devel@nongnu.org>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
	"Daniel P. Berrangé" <berrange@redhat.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Eric Blake" <eblake@redhat.com>,
	"Markus Armbruster" <armbru@redhat.com>,
	"Marcelo Tosatti" <mtosatti@redhat.com>,
	"Zhao Liu" <zhao1.liu@intel.com>,
	"Nikunj A Dadhania" <nikunj@amd.com>,
	"Tom Lendacky" <thomas.lendacky@amd.com>,
	"Michael Roth" <michael.roth@amd.com>,
	"Roy Hopkins" <roy.hopkins@randomman.co.uk>,
	"Srikanth Aithal" <srikanth.aithal@amd.com>
Subject: [PATCH v3 0/9] target/i386: SEV: Add support for enabling VMSA SEV features
Date: Tue, 28 Oct 2025 16:13:25 +0530	[thread overview]
Message-ID: <cover.1761648149.git.naveen@kernel.org> (raw)

This series adds support for enabling VMSA SEV features for SEV-ES and 
SEV-SNP guests through the Qemu command line. This is already supported 
for IGVM files, so some of that code has been generalized and reused.

Debug-swap is already supported in KVM today, while patches for enabling 
Secure TSC have been accepted for the upcoming kernel release.

I have tested this with a simple IGVM file generated by the buildigvm 
tool, and it did not show any issues with IGVM compatibility.


- Naveen

---
v2: http://lore.kernel.org/r/cover.1758794556.git.naveen@kernel.org

Changes since v2:
- Clarify that debug-swap property only works for SEV-ES/SEV-SNP guests, 
  and update commit log to clarify the same (Markus)
- Update commit log to clarify need for a new tsc-frequency property and 
  its interaction with the one on the cpu object (Tom)


Naveen N Rao (AMD) (9):
  target/i386: SEV: Generalize handling of SVM_SEV_FEAT_SNP_ACTIVE
  target/i386: SEV: Ensure SEV features are only set through qemu cli or
    IGVM
  target/i386: SEV: Consolidate SEV feature validation to common init
    path
  target/i386: SEV: Validate that SEV-ES is enabled when VMSA features
    are used
  target/i386: SEV: Enable use of KVM_SEV_INIT2 for SEV-ES guests
  target/i386: SEV: Add support for enabling debug-swap SEV feature
  target/i386: SEV: Add support for enabling Secure TSC SEV feature
  target/i386: SEV: Add support for setting TSC frequency for Secure TSC
  target/i386: SEV: Refactor check_sev_features()

 target/i386/sev.h |   4 +-
 target/i386/sev.c | 171 +++++++++++++++++++++++++++++++++++++---------
 qapi/qom.json     |  17 ++++-
 3 files changed, 157 insertions(+), 35 deletions(-)


base-commit: 36076d24f04ea9dc3357c0fbe7bb14917375819c
-- 
2.51.0



             reply	other threads:[~2025-10-28 10:45 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-28 10:43 Naveen N Rao (AMD) [this message]
2025-10-28 10:43 ` [PATCH v3 1/9] target/i386: SEV: Generalize handling of SVM_SEV_FEAT_SNP_ACTIVE Naveen N Rao (AMD)
2025-10-28 10:43 ` [PATCH v3 2/9] target/i386: SEV: Ensure SEV features are only set through qemu cli or IGVM Naveen N Rao (AMD)
2025-10-28 10:43 ` [PATCH v3 3/9] target/i386: SEV: Consolidate SEV feature validation to common init path Naveen N Rao (AMD)
2025-10-28 10:43 ` [PATCH v3 4/9] target/i386: SEV: Validate that SEV-ES is enabled when VMSA features are used Naveen N Rao (AMD)
2025-10-28 10:43 ` [PATCH v3 5/9] target/i386: SEV: Enable use of KVM_SEV_INIT2 for SEV-ES guests Naveen N Rao (AMD)
2025-10-28 10:43 ` [PATCH v3 6/9] target/i386: SEV: Add support for enabling debug-swap SEV feature Naveen N Rao (AMD)
2025-10-28 10:43 ` [PATCH v3 7/9] target/i386: SEV: Add support for enabling Secure TSC " Naveen N Rao (AMD)
2025-10-28 10:43 ` [PATCH v3 8/9] target/i386: SEV: Add support for setting TSC frequency for Secure TSC Naveen N Rao (AMD)
2025-11-06 12:09   ` Markus Armbruster
2025-11-07  8:51     ` Naveen N Rao
2025-11-07  9:49       ` Markus Armbruster
2025-11-10 10:18         ` Naveen N Rao
2025-11-07  9:59       ` Daniel P. Berrangé
2025-11-10 10:12         ` Naveen N Rao
2025-10-28 10:43 ` [PATCH v3 9/9] target/i386: SEV: Refactor check_sev_features() Naveen N Rao (AMD)

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=cover.1761648149.git.naveen@kernel.org \
    --to=naveen@kernel.org \
    --cc=armbru@redhat.com \
    --cc=berrange@redhat.com \
    --cc=eblake@redhat.com \
    --cc=eduardo@habkost.net \
    --cc=michael.roth@amd.com \
    --cc=mtosatti@redhat.com \
    --cc=nikunj@amd.com \
    --cc=pbonzini@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=roy.hopkins@randomman.co.uk \
    --cc=srikanth.aithal@amd.com \
    --cc=thomas.lendacky@amd.com \
    --cc=zhao1.liu@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.