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There are mainly two places where this is problematic: (a) When vCPUs switch on a pCPU or pCPUs (b) When domu mapped pages onto dom0, are to be unmapped, then each page being removed by XENMEM_remove_from_physmap has its TLBs invalidated by the TLBI variant that flushes the whole range. This patch series prefers usage of IPA-based TLBIs wherever possible instead of complete flushing of TLBs every time. It consists of three patches where the first one address the issue being discussed for Arm64. Second patch further optimizes the combined stage-1,2 TLB flushes by leveraging FEAT_nTLBPA. Third patch introduces IPA-based TLBI for Arm32 in presence of FEAT_nTLBPA. Haseeb Ashraf (3): xen/arm/p2m: perform IPA-based TLBI when IPA is known xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA xen/arm32: add CPU capability for IPA-based TLBI Changes in v3: - Mainly the handling of repeat TLBI workaround with IPA-based TLBI, so that the extra TLBI and DSB are repeated only for the final TLBI and DSB of the whole sequence. - Updated code comments as per feedback. Further details are available in each commit's changelog. - Minor updates to code as per feedback. Further details are available in each commit's changelog. Changes in v2: - Split up the commit in 3 commits. First commit implements the baseline implementation without any addition of new CPU capabilities. Implemented new CPU caps in separate features to emphasize how each of it optimizes the TLB invalidation. - Moved ARM32 and ARM64 specific implementations of TLBIs to architecture specific flushtlb.h. - Added references of ARM ARM in code comments. - Evaluated and added a threshold to select between IPA-based TLB invalidation vs fallback to full stage TLB invalidation above the threshold. - Introduced ARM_HAS_NTLBPA CPU capability which leverages FEAT_nTLBPA for arm32 as well as arm64. - Introduced ARM_HAS_TLB_IPA CPU capability for IPA-based TLBI for arm32. Haseeb Ashraf (3): xen/arm/p2m: perform IPA-based TLBI when IPA is known xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA xen/arm32: add CPU capability for IPA-based TLBI xen/arch/arm/cpufeature.c | 31 ++++++++ xen/arch/arm/include/asm/arm32/flushtlb.h | 87 +++++++++++++++++++++ xen/arch/arm/include/asm/arm64/flushtlb.h | 77 +++++++++++++++++++ xen/arch/arm/include/asm/cpregs.h | 4 + xen/arch/arm/include/asm/cpufeature.h | 27 ++++++- xen/arch/arm/include/asm/mmu/p2m.h | 2 + xen/arch/arm/include/asm/processor.h | 10 +++ xen/arch/arm/mmu/p2m.c | 92 +++++++++++++++++------ 8 files changed, 302 insertions(+), 28 deletions(-) -- 2.43.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 471EFD4A5F4 for ; Sun, 18 Jan 2026 13:34:26 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.1207809.1520173 (Exim 4.92) (envelope-from ) id 1vhSul-0003pS-L1; Sun, 18 Jan 2026 13:33:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1207809.1520173; Sun, 18 Jan 2026 13:33:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vhSul-0003pJ-Ep; Sun, 18 Jan 2026 13:33:59 +0000 Received: by outflank-mailman (input) for mailman id 1207809; Sun, 18 Jan 2026 13:33:58 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vhSuk-0003p9-1c for xen-devel@lists.xenproject.org; Sun, 18 Jan 2026 13:33:58 +0000 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [2a00:1450:4864:20::52c]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 5417a52e-f472-11f0-9ccf-f158ae23cfc8; Sun, 18 Jan 2026 14:33:54 +0100 (CET) Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-64b921d9e67so5818392a12.3 for ; Sun, 18 Jan 2026 05:33:52 -0800 (PST) Received: from PKL-HASEEBA-LT.. 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There are mainly two places where this is problematic: (a) When vCPUs switch on a pCPU or pCPUs (b) When domu mapped pages onto dom0, are to be unmapped, then each page being removed by XENMEM_remove_from_physmap has its TLBs invalidated by the TLBI variant that flushes the whole range. This patch series prefers usage of IPA-based TLBIs wherever possible instead of complete flushing of TLBs every time. It consists of three patches where the first one address the issue being discussed for Arm64. Second patch further optimizes the combined stage-1,2 TLB flushes by leveraging FEAT_nTLBPA. Third patch introduces IPA-based TLBI for Arm32 in presence of FEAT_nTLBPA. Haseeb Ashraf (3): xen/arm/p2m: perform IPA-based TLBI when IPA is known xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA xen/arm32: add CPU capability for IPA-based TLBI Changes in v3: - Mainly the handling of repeat TLBI workaround with IPA-based TLBI, so that the extra TLBI and DSB are repeated only for the final TLBI and DSB of the whole sequence. - Updated code comments as per feedback. Further details are available in each commit's changelog. - Minor updates to code as per feedback. Further details are available in each commit's changelog. Changes in v2: - Split up the commit in 3 commits. First commit implements the baseline implementation without any addition of new CPU capabilities. Implemented new CPU caps in separate features to emphasize how each of it optimizes the TLB invalidation. - Moved ARM32 and ARM64 specific implementations of TLBIs to architecture specific flushtlb.h. - Added references of ARM ARM in code comments. - Evaluated and added a threshold to select between IPA-based TLB invalidation vs fallback to full stage TLB invalidation above the threshold. - Introduced ARM_HAS_NTLBPA CPU capability which leverages FEAT_nTLBPA for arm32 as well as arm64. - Introduced ARM_HAS_TLB_IPA CPU capability for IPA-based TLBI for arm32. Haseeb Ashraf (3): xen/arm/p2m: perform IPA-based TLBI when IPA is known xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA xen/arm32: add CPU capability for IPA-based TLBI xen/arch/arm/cpufeature.c | 31 ++++++++ xen/arch/arm/include/asm/arm32/flushtlb.h | 87 +++++++++++++++++++++ xen/arch/arm/include/asm/arm64/flushtlb.h | 77 +++++++++++++++++++ xen/arch/arm/include/asm/cpregs.h | 4 + xen/arch/arm/include/asm/cpufeature.h | 27 ++++++- xen/arch/arm/include/asm/mmu/p2m.h | 2 + xen/arch/arm/include/asm/processor.h | 10 +++ xen/arch/arm/mmu/p2m.c | 92 +++++++++++++++++------ 8 files changed, 302 insertions(+), 28 deletions(-) -- 2.43.0