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Tue, 03 Feb 2026 06:27:22 -0800 (PST) Received: from ZEVORN-PC.bbrouter ([38.95.120.198]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b7a1af898asm24194529eec.33.2026.02.03.06.27.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 06:27:21 -0800 (PST) From: chao.liu.zevorn@gmail.com To: Alistair Francis , Daniel Henrique Barboza , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Tao Tang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, hust-os-kernel-patches@googlegroups.com, Chao Liu Subject: [PATCH v3 0/2] tests/qtest: Add RISC-V IOMMU bare-metal test using iommu-testdev Date: Tue, 3 Feb 2026 22:27:04 +0800 Message-ID: X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1342; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Chao Liu Hi, This patch series adds a bare-metal qtest for the RISC-V IOMMU using the iommu-testdev framework. The test exercises address translation paths without requiring a full guest OS boot. Motivation ---------- The existing RISC-V IOMMU qtest (riscv-iommu-test.c) focuses on PCI device enumeration and register-level validation: - PCI configuration space verification (vendor/device ID) - Register reset value checks - Queue initialization procedures (CQ/FQ/PQ) However, it does not test the actual address translation functionality. This new test fills that gap by using iommu-testdev to trigger DMA transactions and validate the IOMMU's translation logic. Comparison with Existing Test ----------------------------- | Feature | riscv-iommu-test.c | iommu-riscv-test.c (new) | |-----------------------|--------------------|--------------------------| | PCI config | Yes | No | | Register reset | Yes | No | | Queue init | Yes | Yes (via helper) | | Bare translation | No | Yes | | S-stage (SV39) | No | Yes | | G-stage (SV39x4) | No | Yes | | Nested translation | No | Yes | | DMA verification | No | Yes | | Uses iommu-testdev | No | Yes | The new test provides: - Device context (DC) configuration and validation - SV39 page table walks for S-stage translation - SV39x4 page table walks for G-stage translation - Nested translation combining both stages - FCTL register constraint validation - End-to-end DMA verification Note: The current implementation only supports SV39/SV39x4. Support for SV48/SV48x4/SV57/SV57x4 can be added in future patches. Testing ------- QTEST_QEMU_BINARY=./build/qemu-system-riscv64 \ ./build/tests/qtest/iommu-riscv-test --tap -k Changes v2 -> v3 ---------------- - Removed duplicate header includes in both patches (Tao) - Fixed memory leak of state->iommu_dev and state->testdev in riscv_iommu_test_setup() in patch 2 (Fabiano) Changes v1 -> v2 ---------------- - Removed unused 'mode' parameter from qriommu_get_pte_attrs() function - Simplified PTE mask definitions in header file by using direct hex values instead of individual bit defines (removed QRIOMMU_PTE_V/R/W/X /U/G/A/D macros), added comment referencing target/riscv/cpu_bits.h - Cleaned up variable declarations in qriommu_setup_translation_tables() to follow C99 style (declare at point of use) - Minor code style improvements Thanks, Chao Chao Liu (2): tests/qtest/libqos: Add RISC-V IOMMU helper library tests/qtest: Add RISC-V IOMMU bare-metal test MAINTAINERS | 2 + tests/qtest/iommu-riscv-test.c | 279 +++++++++++++++++++ tests/qtest/libqos/meson.build | 2 +- tests/qtest/libqos/qos-riscv-iommu.c | 403 +++++++++++++++++++++++++++ tests/qtest/libqos/qos-riscv-iommu.h | 164 +++++++++++ tests/qtest/meson.build | 5 +- 6 files changed, 853 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/iommu-riscv-test.c create mode 100644 tests/qtest/libqos/qos-riscv-iommu.c create mode 100644 tests/qtest/libqos/qos-riscv-iommu.h -- 2.53.0