From: Tao Ding <dingtao0430@163.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Tao Ding <dingtao0430@163.com>
Subject: [PATCH v2 0/1] Fix transfer size register decrement
Date: Tue, 24 Mar 2026 00:50:06 +0800 [thread overview]
Message-ID: <cover.1774282897.git.dingtao0430@163.com> (raw)
In-Reply-To: <7e7677f4-9cd9-4d33-995e-f7645786e1ce@163.com>
When source and destination widths are different, the transfer size
register was not being decremented correctly, causing data corruption.
Compared to the previous version(PATCH v1 2/3), simplified the code and
the judgment of constraint relationships between size, swidth, and dwidth has been added.
Tao Ding (1):
Fix transfer size register decrement in pl080
hw/dma/pl080.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
base-commit: 8e711856d7639cbffa51405f2cc2366e3d9e3a23
--
2.43.0
next prev parent reply other threads:[~2026-03-23 16:51 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-12 8:02 [PATCH v1 0/3] Fixed bugs in pl080 Tao Ding
2026-03-12 8:02 ` [PATCH v1 1/3] An interrupt is generated after the DMA transfer complete Tao Ding
2026-03-12 8:02 ` [PATCH v1 2/3] The swidth and dwidth of pl080 are not equal Tao Ding
2026-03-13 12:20 ` Peter Maydell
2026-03-14 17:14 ` Tao Ding
2026-03-23 16:50 ` Tao Ding [this message]
2026-03-23 16:50 ` [PATCH v2 1/1] Fix transfer size register decrement in pl080 Tao Ding
2026-03-24 12:01 ` Peter Maydell
2026-03-12 8:02 ` [PATCH v1 3/3] The LLI of pl080 should be aligned with 4 bytes Tao Ding
2026-03-13 11:26 ` Peter Maydell
2026-03-13 12:35 ` [PATCH v1 0/3] Fixed bugs in pl080 Peter Maydell
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