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Tsirkin" , Jason Wang , Yi Liu , =?UTF-8?q?Cl=C3=A9ment=20Mathieu--Drif?= , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Tao Tang Cc: qemu-devel@nongnu.org, Chao Liu , Fengyuan Yu <15fengyuan@gmail.com> Subject: [PATCH v3 0/2] tests/qtest: Add Intel IOMMU bare-metal test using iommu-testdev Date: Wed, 25 Mar 2026 15:09:04 +0800 Message-Id: X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=15fengyuan@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This patch series adds a bare-metal qtest for the Intel IOMMU (VT-d) using the iommu-testdev framework. The test exercises address translation paths without requiring a full guest OS boot. Motivation ---------- The Intel IOMMU implementation in QEMU supports various translation modes. Currently, comprehensive testing of these translation paths requires booting a full guest OS with appropriate drivers, which is time-consuming and makes regression testing difficult. This new test fills that gap by using iommu-testdev to trigger DMA transactions and validate the IOMMU's translation logic directly. Test Coverage ------------- The new test provides: - Legacy pass-through mode (identity mapping) - Legacy translated mode with 4-level second-level page table walks - Scalable pass-through mode (PGTT=100b) - Scalable second-level translation mode (PGTT=010b) - Scalable first-level translation mode (PGTT=001b) - Root/Context Entry, PASID Directory/Table Entry configuration - Complete 48-bit address space translation - End-to-end DMA verification with memory validation Testing ------- QTEST_QEMU_BINARY=./build/qemu-system-x86_64 \ ./build/tests/qtest/iommu-intel-test --tap -k Changes v1 -> v2 ---------------- - Rebase onto latest upstream to resolve compilation errors - Add scalable translation mode tests (SLT, FLT, PassThrough) - Add spec-aligned register field comments for improved readability Changes v2 -> v3 ---------------- - Fix MAINTAINERS: move qos-intel-iommu* to "QTest IOMMU helpers" section, move iommu-intel-test.c entry to patch 2/2, remove duplicate entries from x86 general section - Remove duplicate Q35_IOMMU_BASE macro, use existing Q35_HOST_BRIDGE_IOMMU_ADDR instead - Drop unused QVTD_TM_SCALABLE_NESTED enum value - Fix parameter alignment in function declarations - Clarify qvtd_build_dma_attrs() comment: PASID=0 is reached via VT-d's no-PASID fallback, not via DMA attributes Thanks, Fengyuan Fengyuan Yu (2): tests/qtest/libqos: Add Intel IOMMU helper library tests/qtest: Add Intel IOMMU bare-metal test MAINTAINERS | 2 + tests/qtest/iommu-intel-test.c | 216 +++++++++++++ tests/qtest/libqos/meson.build | 3 + tests/qtest/libqos/qos-intel-iommu.c | 454 +++++++++++++++++++++++++++ tests/qtest/libqos/qos-intel-iommu.h | 185 +++++++++++ tests/qtest/meson.build | 2 + 6 files changed, 862 insertions(+) create mode 100644 tests/qtest/iommu-intel-test.c create mode 100644 tests/qtest/libqos/qos-intel-iommu.c create mode 100644 tests/qtest/libqos/qos-intel-iommu.h -- 2.39.5