From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 295813EC2EF for ; Wed, 27 May 2026 09:34:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779874501; cv=none; b=MJtwT55mmax2lQugLyNzv4+ZhC7h23p8nGDvKdyB65g50GzUu5IafQJgZ5whfeoKb7dcqBlzvumkYBbTFpT5XMIUvKMXFHKiPtOB1vf1t1h5TmJ2WD0slx75WK4fGKTqND+0IiEGHHqS+TOTOaCEW+U/uPr1w79LvtjnKzaco2o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779874501; c=relaxed/simple; bh=zohuggykXlTUG/2S9hJbrMgZhDLRXdILpg6TaqEydBw=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=EuNbKzA088WcJ3MnkScTap94XygAaMohL8SD3X8ZRazBuzVHh7YFQcwqSY6un1JqOvwcbs7leQsbRAMWmMjtjO1xUSmNlPClJxNQrpIdmEWyx6g830hDwopvOtwTsBKMHRo0Nt9jAzV4CprhufmJkWsZ/keI3U95CstQSxOLEO4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cCF5wHTZ; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cCF5wHTZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779874499; x=1811410499; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=zohuggykXlTUG/2S9hJbrMgZhDLRXdILpg6TaqEydBw=; b=cCF5wHTZuDOGxFeprSQMfLl96Kme/5+7rnzHjzmJ5IBP0WAPLkNiKMor ihi5AXIQjZbwyJkqmRcDZmXC3fXyhsYc/ldAvRqAynlOk8CbXsKjB9KGY aztf2i7mH9n2BoxcPh2iIsl9TLdjPIPfo1EG+ORc8OiqF30A4d8u3d2GI IrrJfhh4JH7f8vjNiryvKF7pJW0P4hrZr2V4D42eVQYS2FMTsd/jZ/wTn /OXZH9OKrHHr2kGZXVfHZClIx9mHhUCX/7CFTi6fm5nn87mnck1i5bYSi 3JRTVZ/xVBisiLlltbDLermwmoQOac8A0DybSFHFiBVvHQwl3+tjxAHsh Q==; X-CSE-ConnectionGUID: Hdn9eiVqSMSTbdOCfv0j7A== X-CSE-MsgGUID: T5HwN5PxQaSrmQdqex2WAg== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="80548819" X-IronPort-AV: E=Sophos;i="6.24,171,1774335600"; d="scan'208";a="80548819" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2026 02:34:58 -0700 X-CSE-ConnectionGUID: CZIrIWH1RberkFTSJvMOlA== X-CSE-MsgGUID: Ofq1tCegQxK83r3wgwAqjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,171,1774335600"; d="scan'208";a="246211843" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by orviesa003.jf.intel.com with ESMTP; 27 May 2026 02:34:55 -0700 From: Chen Yu To: tony.luck@intel.com, reinette.chatre@intel.com Cc: x86@kernel.org, linux-kernel@vger.kernel.org, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, Dave.Martin@arm.com, james.morse@arm.com, babu.moger@amd.com, fenghuay@nvidia.com Subject: [RFC PATCH 0/6] x86/resctrl: Introduce MMIO-based CMT access for Enhanced RDT Date: Wed, 27 May 2026 17:25:56 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Intel Enhanced Resource Director Technology (ERDT) extends the existing RDT framework with two major capabilities: 1. MMIO-based access to monitoring and allocation registers, replacing the legacy MSR-based interface. 2. Region-aware RDT for fine-grained control over different tiers of memory (e.g., CXL.mem, DDR). This is described in the Intel RDT Architecture Specification: https://cdrdv2-public.intel.com/789566/356688-intel-rdt-arch-spec.pdf This patch set focuses on the first part: enabling MMIO-based access for Cache Monitoring Technology (CMT), while CAT/MBM/MBA are still using MSR. The platform advertises the MMIO register layout through the ACPI ERDT (Enhanced Resource Director Technology) table, which contains sub-tables describing per-domain register regions for monitoring and allocation. With ERDT, L3 cache occupancy counters are read via MMIO rather than MSR, allowing the reads to be performed from any CPU without requiring cross-CPU IPIs. This series parses the relevant ACPI sub-tables (RMDD, CMRC), prepares the resctrl monitor infrastructure for MMIO-based reads, and adds initial support for reading L3 occupancy via the CMRC interface. kselftest of CMT and L3_CAT has passed with minor adjustment at https://lore.kernel.org/lkml/20260523101715.3964456-1-yu.c.chen@intel.com/. Anil S Keshavamurthy (1): x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID Chen Yu (4): x86/resctrl: Parse ACPI CMRC table x86/resctrl: Rename prev_msr to prev_mon_val x86/resctrl: Refactor the monitor read function x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO read Tony Luck (1): fs/resctrl: Do not invoke smp_processor_id() in preemptible context arch/x86/Kconfig | 4 +- arch/x86/include/asm/resctrl.h | 4 + arch/x86/kernel/cpu/resctrl/Makefile | 1 + arch/x86/kernel/cpu/resctrl/core.c | 5 +- arch/x86/kernel/cpu/resctrl/erdt.c | 451 +++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 11 +- arch/x86/kernel/cpu/resctrl/monitor.c | 64 ++-- fs/resctrl/monitor.c | 38 ++- 8 files changed, 538 insertions(+), 40 deletions(-) create mode 100644 arch/x86/kernel/cpu/resctrl/erdt.c -- 2.25.1