From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEBEE1D9A5F for ; Sat, 6 Jun 2026 02:41:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780713680; cv=none; b=QTXiyZ+yfZlTmwqJSJ9OBz6SPwJjpnPiU30KeLnfTwWgU44u9dR830KnjGGEheXdrysA5f2Wrzf2wD3ggwg0C9UcwA2gz+w5HQ+n789jj8ztmNlHcFYHmePu3E4ssbZ2FwtaI26gztmHGO1DSdnIT/aptsF3rj1FQrZs1E6HDt0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780713680; c=relaxed/simple; bh=SOT81aUDfNt/Qxow2a2MoWOLATzd6fxjxbX68u0wJ4w=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=rDna3hOIN+L63OTswv0IyQFZV4ozrv/vrZYPUlEA+wTZEJJVrdJvFlMXyge+PpTzHBJhinzLZkHTUmQu5bfKievfhTNUD97yRQjE1Am25R8SNtEZk4IK4AmcxXMXBG1cAXmguoD1b8cWDzCr+wKkiOh57OrkBz6YBaw3HQ8tC70= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ghc9xMl2; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ghc9xMl2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780713679; x=1812249679; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=SOT81aUDfNt/Qxow2a2MoWOLATzd6fxjxbX68u0wJ4w=; b=ghc9xMl2KKf+lBv6RO56IVUPmIqwJhA+oinKeY6CfF9VoDrEus+04f4K CfSwIXYGN79eD6Wwqo8q2DnplLe9vrNsyZLBvXzHgLrjPRIgefVT7sFK/ u9QEY5UkdpUAodJgwFii2+EKggXP2zopDS4Jd+3Tc+/JiqcUG/yj/n5bQ n4v4RxW12rteWuGxFqf1wlIB0pjy8QloMZeRbQvYEeMeEZx550WgcLu8h edWlEB2Hm9KYPAG3oBpmvqTx1uisYPv8hQOqf8MsEic6dQ+e1PBEDi/CB ZgNgo6MqNdy1Nv98wauIjgIj+s7lb0ddG2nHDHUQdvdJpFcI7dyqz/JnC A==; X-CSE-ConnectionGUID: lzIBTbYDS5WPxyrRMvMkTA== X-CSE-MsgGUID: N7adi0AqTM+9XD1GrHXfVQ== X-IronPort-AV: E=McAfee;i="6800,10657,11808"; a="85434286" X-IronPort-AV: E=Sophos;i="6.24,189,1774335600"; d="scan'208";a="85434286" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2026 19:41:18 -0700 X-CSE-ConnectionGUID: hgYibrbDR5mAyt9R8NHypA== X-CSE-MsgGUID: Ocmz8SM4QVmzngxClQf2KQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,189,1774335600"; d="scan'208";a="249939727" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by orviesa005.jf.intel.com with ESMTP; 05 Jun 2026 19:41:15 -0700 From: Chen Yu To: tony.luck@intel.com, reinette.chatre@intel.com Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de, tglx@kernel.org, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, dave.martin@arm.com, james.morse@arm.com, fenghuay@nvidia.com, babu.moger@amd.com, anil.keshavamurthy@broadcom.com Subject: [PATCH v3 0/6] Introduce MMIO-based CMT access for Enhanced RDT Date: Sat, 6 Jun 2026 10:31:26 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Intel Enhanced Resource Director Technology (ERDT) extends the existing RDT framework with two major capabilities: 1. MMIO-based access to monitoring and allocation registers, replacing the legacy MSR-based interface. 2. Region-aware RDT for fine-grained control over different tiers of memory (e.g., CXL.mem, DDR). This is described in the Intel RDT Architecture Specification: https://cdrdv2-public.intel.com/789566/356688-intel-rdt-arch-spec.pdf This patch set focuses on the first part: enabling MMIO-based access for Cache Monitoring Technology (CMT), while CAT/MBM/MBA are still using MSR. The platform advertises the MMIO register layout through the ACPI ERDT (Enhanced Resource Director Technology) table, which contains sub-tables describing per-domain register regions for monitoring and allocation. With ERDT, L3 cache occupancy counters are read via MMIO rather than MSR, allowing the reads to be performed from any CPU without requiring cross-CPU IPIs. This series parses the relevant ACPI sub-tables (RMDD, CMRC), prepares the resctrl monitor infrastructure for MMIO-based reads, and adds initial support for reading L3 occupancy via the CMRC interface. kselftest of CMT and L3_CAT has passed with minor adjustment at https://lore.kernel.org/lkml/20260523101715.3964456-1-yu.c.chen@intel.com/. Changes from V2 to V3: - Wrap __resctrl_arch_late_init() to avoid the goto logic. (Thomas Gleixner) - Make the variables in struct erdt_domain_info tabular format (Thomas Gleixner) - Remove tail comments (Thomas Gleixner) - Make the name of erdt_enabled() and variable in it consistent and comprehensible. (Thomas Gleixner) - Use topo_lookup_cpuid() to search the CPU id according to the x2apic id (Thomas Gleixner) - Fix kernel doc comment format (Thomas Gleixner) - Use brackets for multiple lines "if" case. (Thomas Gleixner) - Let the parameter for cacd_init() to fully utilize 100 characters. (Thomas Gleixner) - Variables are reordered in reverse fir-tree.(Thomas Gleixner) - Added a named constant and use it in the rmdd->flags check. (Thomas Gleixner) - Introduce helper functions to make the code readable when iterating the RMDD tables. (Thomas Gleixner) - Make the macros tabular format. (Thomas Gleixner) Changes from V1 to V2: - Add #include to follow the "include-what-you-use" best practice (Tony Luck) - Fix 3 issues reported by: https://sashiko.dev/#/patchset/cover.1779872016.git.yu.c.chen%40intel.com Remove the variable of cacd in struct erdt_domain_info as it will never be used after initialization. Invoke erdt_exit() to avoid resource leak if rdt_alloc_capable and rdt_mon_capable are both false. Adjust the comments suggested by sashiko. Anil S Keshavamurthy (1): x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID Chen Yu (4): x86/resctrl: Parse ACPI CMRC table x86/resctrl: Rename prev_msr to prev_mon_val x86/resctrl: Refactor the monitor read function x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO read Tony Luck (1): fs/resctrl: Do not invoke smp_processor_id() in preemptible context arch/x86/Kconfig | 4 +- arch/x86/include/asm/apic.h | 1 + arch/x86/include/asm/resctrl.h | 4 + arch/x86/kernel/cpu/resctrl/Makefile | 1 + arch/x86/kernel/cpu/resctrl/core.c | 16 +- arch/x86/kernel/cpu/resctrl/erdt.c | 433 +++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 11 +- arch/x86/kernel/cpu/resctrl/monitor.c | 64 ++-- arch/x86/kernel/cpu/topology.c | 2 +- fs/resctrl/monitor.c | 41 ++- 10 files changed, 535 insertions(+), 42 deletions(-) create mode 100644 arch/x86/kernel/cpu/resctrl/erdt.c -- 2.25.1