* [PATCH 0/9] arm64: zynqmp: DT updates
@ 2026-06-09 7:48 Michal Simek
2026-06-09 7:48 ` [PATCH 1/9] arm64: zynqmp-dlc21-revA: Update GPIO line names mapping Michal Simek
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Michal Simek @ 2026-06-09 7:48 UTC (permalink / raw)
To: u-boot, git
Cc: Nithish Kumar Naroju, Padmarao Begari, Radhey Shyam Pandey,
Rob Herring (Arm), Rohit Visavalia, Shaikh Mohammed Suhan,
Tom Rini, Trapti Damodar Balgi
Hi,
sending multiple patches to update DTs for ZynqMP targets to reflect
the latest findings and updates.
Thanks,
Michal
Michal Simek (5):
arm64: zynqmp: Drop incorrect #phy-cells from ethernet-phy nodes
arm64: zynqmp: Use fixed-partitions for MTD
arm64: zynqmp: Add CMA reserved-memory for runtime FPGA loading
arm64: zynqmp: dts: Fix file descriptions to match actual filenames
arm64: zynqmp: Sync compatible string format
Rob Herring (Arm) (1):
arm64: dts: xilinx: Drop "label" property on dlg,slg7xl45106
Shaikh Mohammed Suhan (1):
arm64: zynqmp: add USB hub supply regulators
Trapti Damodar Balgi (2):
arm64: zynqmp-dlc21-revA: Update GPIO line names mapping
arm64: zynqmp-dlc21-revA: add mac nvmem cell for gem0
arch/arm/dts/zynqmp-dlc21-revA.dts | 17 +-
arch/arm/dts/zynqmp-sc-revB.dts | 171 +++++++++---------
arch/arm/dts/zynqmp-sc-revC.dts | 1 -
arch/arm/dts/zynqmp-sc-vek280-revA.dtso | 5 +-
arch/arm/dts/zynqmp-sc-vek280-revB.dtso | 5 +-
arch/arm/dts/zynqmp-sc-vhk158-revA.dtso | 5 +-
arch/arm/dts/zynqmp-sc-vpk120-revB.dtso | 5 +-
arch/arm/dts/zynqmp-sc-vpk180-revA.dtso | 5 +-
arch/arm/dts/zynqmp-sc-vpk180-revB.dtso | 7 +-
arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 22 ++-
arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 25 ++-
arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 25 ++-
arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 21 ++-
arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 23 ++-
arch/arm/dts/zynqmp-sm-k24-revA.dts | 7 +-
arch/arm/dts/zynqmp-sm-k26-revA.dts | 11 +-
.../zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 38 ++--
arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 14 +-
arch/arm/dts/zynqmp-vpk120-revA.dts | 14 +-
arch/arm/dts/zynqmp-zc1232-revA.dts | 55 ++++--
arch/arm/dts/zynqmp-zc1254-revA.dts | 53 ++++--
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 55 ++++--
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 153 +++++++++-------
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 124 +++++++------
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 53 ++++--
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 15 ++
arch/arm/dts/zynqmp-zcu100-revC.dts | 17 +-
arch/arm/dts/zynqmp-zcu102-revA.dts | 56 ++++--
arch/arm/dts/zynqmp-zcu102-revB.dts | 1 -
arch/arm/dts/zynqmp-zcu104-revA.dts | 56 ++++--
arch/arm/dts/zynqmp-zcu104-revC.dts | 56 ++++--
arch/arm/dts/zynqmp-zcu106-revA.dts | 56 ++++--
arch/arm/dts/zynqmp-zcu111-revA.dts | 56 ++++--
arch/arm/dts/zynqmp-zcu1275-revA.dts | 53 ++++--
arch/arm/dts/zynqmp-zcu1275-revB.dts | 53 ++++--
arch/arm/dts/zynqmp-zcu1285-revA.dts | 15 ++
arch/arm/dts/zynqmp-zcu208-revA.dts | 16 +-
arch/arm/dts/zynqmp-zcu216-revA.dts | 16 +-
arch/arm/dts/zynqmp-zcu670-revA.dts | 18 +-
arch/arm/dts/zynqmp-zcu670-revB.dts | 18 +-
40 files changed, 948 insertions(+), 468 deletions(-)
--
2.43.0
base-commit: e91911169bc737ee4a79963a1cba8db2aab7c1c0
branch: debian-sent3
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/9] arm64: zynqmp-dlc21-revA: Update GPIO line names mapping
2026-06-09 7:48 [PATCH 0/9] arm64: zynqmp: DT updates Michal Simek
@ 2026-06-09 7:48 ` Michal Simek
2026-06-09 7:48 ` [PATCH 2/9] arm64: zynqmp-dlc21-revA: add mac nvmem cell for gem0 Michal Simek
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2026-06-09 7:48 UTC (permalink / raw)
To: u-boot, git; +Cc: Trapti Damodar Balgi, Tom Rini
From: Trapti Damodar Balgi <traptidamodar.balgi@amd.com>
Update the gpio-line-names property to reflect the latest GPIO mapping,
including PMOD and VCCO labels.
Signed-off-by: Trapti Damodar Balgi <traptidamodar.balgi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/zynqmp-dlc21-revA.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index d48b6f3a8ec8..25cd0a09c944 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -119,10 +119,10 @@
"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
- "", "", "", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 - 89 */
- "", "", "", "", "", /* 90 - 94 */
- "", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
+ "", "", "", "", "PMOD_0", /* 80 - 84 */
+ "PMOD_1", "PMOD_2", "PMOD_3", "PMOD_4", "PMOD_5", /* 85 -89 */
+ "PMOD_6", "PMOD_7", "", "", "", /* 90 - 94 */
+ "", "", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
"VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
"", "", "", "", "", /* 105 - 109 */
"SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/9] arm64: zynqmp-dlc21-revA: add mac nvmem cell for gem0
2026-06-09 7:48 [PATCH 0/9] arm64: zynqmp: DT updates Michal Simek
2026-06-09 7:48 ` [PATCH 1/9] arm64: zynqmp-dlc21-revA: Update GPIO line names mapping Michal Simek
@ 2026-06-09 7:48 ` Michal Simek
2026-06-09 7:48 ` [PATCH 3/9] arm64: zynqmp: Drop incorrect #phy-cells from ethernet-phy nodes Michal Simek
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2026-06-09 7:48 UTC (permalink / raw)
To: u-boot, git; +Cc: Trapti Damodar Balgi, Tom Rini
From: Trapti Damodar Balgi <traptidamodar.balgi@amd.com>
Enable nvmem support for MAC address retrieval from EEPROM for
ethernet@ff0b0000.
Add nvmem-cells and nvmem-cell-names to the GEM0 node, and define a
mac-address@20 cell under the EEPROM node on I2C0.
This allows U-Boot to read the MAC address from EEPROM at offset 0x20.
Signed-off-by: Trapti Damodar Balgi <traptidamodar.balgi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/zynqmp-dlc21-revA.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index 25cd0a09c944..83c39ce1a265 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -90,6 +90,9 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ nvmem-cells = <ð_mac>;
+ nvmem-cell-names = "mac-address";
+
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -153,6 +156,12 @@
eeprom: eeprom@50 { /* u46 */
compatible = "atmel,24c32";
reg = <0x50>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eth_mac: mac-address@20 {
+ reg = <0x20 0x6>;
+ };
};
/* u138 - TUSB320IRWBR - for USB-C */
};
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/9] arm64: zynqmp: Drop incorrect #phy-cells from ethernet-phy nodes
2026-06-09 7:48 [PATCH 0/9] arm64: zynqmp: DT updates Michal Simek
2026-06-09 7:48 ` [PATCH 1/9] arm64: zynqmp-dlc21-revA: Update GPIO line names mapping Michal Simek
2026-06-09 7:48 ` [PATCH 2/9] arm64: zynqmp-dlc21-revA: add mac nvmem cell for gem0 Michal Simek
@ 2026-06-09 7:48 ` Michal Simek
2026-06-09 7:48 ` [PATCH 4/9] arm64: zynqmp: Use fixed-partitions for MTD Michal Simek
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2026-06-09 7:48 UTC (permalink / raw)
To: u-boot, git
Cc: Nithish Kumar Naroju, Radhey Shyam Pandey, Rob Herring (Arm),
Rohit Visavalia, Shaikh Mohammed Suhan, Tom Rini
The #phy-cells property is meant for generic PHY providers
(Documentation/devicetree/bindings/phy/phy-bindings.txt) and is not a
valid property for ethernet-phy nodes. Its presence triggers a
dt-validate warning:
ethernet-phy@x (ethernet-phy-id001c.c816): Unevaluated properties
are not allowed ('#phy-cells' was unexpected)
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/zynqmp-sc-revB.dts | 1 -
arch/arm/dts/zynqmp-sc-revC.dts | 1 -
arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 1 -
arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 2 --
arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 2 --
arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 1 -
arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 1 -
arch/arm/dts/zynqmp-zcu102-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu102-revB.dts | 1 -
arch/arm/dts/zynqmp-zcu104-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu104-revC.dts | 1 -
arch/arm/dts/zynqmp-zcu106-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu111-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu208-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu216-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu670-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu670-revB.dts | 1 -
17 files changed, 19 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
index 6181072c1da1..4367136cae8f 100644
--- a/arch/arm/dts/zynqmp-sc-revB.dts
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -136,7 +136,6 @@
#size-cells = <0>;
phy0: ethernet-phy@1 {
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts
index 530a4a5f080f..b9b192f09864 100644
--- a/arch/arm/dts/zynqmp-sc-revC.dts
+++ b/arch/arm/dts/zynqmp-sc-revC.dts
@@ -23,7 +23,6 @@
#size-cells = <0>;
phy0: ethernet-phy@1 { /* ADI1300 */
- #phy-cells = <1>;
compatible = "ethernet-phy-id0283.bc30";
reg = <1>;
adi,rx-internal-delay-ps = <2400>;
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
index 8342479b108a..021bf8ac26e6 100644
--- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -148,7 +148,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@8 { /* Adin u31 */
- #phy-cells = <1>;
compatible = "ethernet-phy-id0283.bc30";
reg = <8>;
adi,rx-internal-delay-ps = <2000>;
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
index db042ffb4f36..048aeb1e7654 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
@@ -265,7 +265,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@4 { /* u81 */
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <4>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -277,7 +276,6 @@
reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
};
phy1: ethernet-phy@8 { /* u36 */
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <8>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index e3567d0abfe0..2eef6ba7df75 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -266,7 +266,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@4 { /* u81 */
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <4>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -278,7 +277,6 @@
reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
};
phy1: ethernet-phy@8 { /* u36 */
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <8>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
index f93c7460a552..ea947cd2dc02 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
@@ -209,7 +209,6 @@
#size-cells = <0>;
phy0: ethernet-phy@1 {
- #phy-cells = <1>;
reg = <1>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
index 70de6933600e..ea7b9253468e 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
@@ -200,7 +200,6 @@
#size-cells = <0>;
phy0: ethernet-phy@1 {
- #phy-cells = <1>;
reg = <1>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 6b1aea95e65a..3d71742fcbee 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -217,7 +217,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@21 {
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <21>;
ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index 3c28130909bc..bad59d7b1d26 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -19,7 +19,6 @@
phy-handle = <&phyc>;
mdio: mdio {
phyc: ethernet-phy@c {
- #phy-cells = <0x1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 0bfeed4293cb..b4e62bf6bb61 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -126,7 +126,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index a7387f4a0e6f..f7a91402a097 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -131,7 +131,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 7b1097579fc2..5eb5f77220d6 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -217,7 +217,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
- #phy-cells = <1>;
reg = <0xc>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index ba1b63391005..72d331a740fa 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -189,7 +189,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 888f711aad97..70b1e81e304c 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -176,7 +176,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index ccdbf8967aa0..bc0ca24ff050 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -183,7 +183,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts
index 058d6b2e6486..1215babe2146 100644
--- a/arch/arm/dts/zynqmp-zcu670-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revA.dts
@@ -185,7 +185,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts
index 010d412b2027..e91f280e4576 100644
--- a/arch/arm/dts/zynqmp-zcu670-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revB.dts
@@ -185,7 +185,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
- #phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/9] arm64: zynqmp: Use fixed-partitions for MTD
2026-06-09 7:48 [PATCH 0/9] arm64: zynqmp: DT updates Michal Simek
` (2 preceding siblings ...)
2026-06-09 7:48 ` [PATCH 3/9] arm64: zynqmp: Drop incorrect #phy-cells from ethernet-phy nodes Michal Simek
@ 2026-06-09 7:48 ` Michal Simek
2026-06-09 7:48 ` [PATCH 5/9] arm64: zynqmp: Add CMA reserved-memory for runtime FPGA loading Michal Simek
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2026-06-09 7:48 UTC (permalink / raw)
To: u-boot, git
Cc: Nithish Kumar Naroju, Radhey Shyam Pandey, Rohit Visavalia,
Tom Rini
Describe flash and NAND MTD partitions using the fixed-partitions
compatible under a dedicated partitions subnode. U-Boot only creates
slave MTD devices from this binding in add_mtd_partitions_of(), so
mtd list can show named partitions.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/zynqmp-sc-revB.dts | 170 +++++++++---------
.../zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 38 ++--
arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 14 +-
arch/arm/dts/zynqmp-vpk120-revA.dts | 14 +-
arch/arm/dts/zynqmp-zc1232-revA.dts | 40 +++--
arch/arm/dts/zynqmp-zc1254-revA.dts | 38 ++--
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 38 ++--
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 136 +++++++-------
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 109 +++++------
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 38 ++--
arch/arm/dts/zynqmp-zcu102-revA.dts | 38 ++--
arch/arm/dts/zynqmp-zcu104-revA.dts | 38 ++--
arch/arm/dts/zynqmp-zcu104-revC.dts | 38 ++--
arch/arm/dts/zynqmp-zcu106-revA.dts | 38 ++--
arch/arm/dts/zynqmp-zcu111-revA.dts | 38 ++--
arch/arm/dts/zynqmp-zcu1275-revA.dts | 38 ++--
arch/arm/dts/zynqmp-zcu1275-revB.dts | 38 ++--
17 files changed, 491 insertions(+), 410 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
index 4367136cae8f..afaecfa5a27a 100644
--- a/arch/arm/dts/zynqmp-sc-revB.dts
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -193,93 +193,97 @@
/* QSPI should also have PINCTRL setup */
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>; /* 40MHz */
- partition@0 {
- label = "Image Selector";
- reg = <0x0 0x80000>; /* 512KB */
- read-only;
- lock;
- };
- partition@80000 {
- label = "Image Selector Golden";
- reg = <0x80000 0x80000>; /* 512KB */
- read-only;
- lock;
- };
- partition@100000 {
- label = "Persistent Register";
- reg = <0x100000 0x20000>; /* 128KB */
- };
- partition@120000 {
- label = "Persistent Register Backup";
- reg = <0x120000 0x20000>; /* 128KB */
- };
- partition@140000 {
- label = "Open_1";
- reg = <0x140000 0xc0000>; /* 768KB */
- };
- partition@200000 {
- label = "Image A (FSBL, PMU, ATF, U-Boot)";
- reg = <0x200000 0xd00000>; /* 13MB */
- };
- partition@f00000 {
- label = "ImgSel Image A Catch";
- reg = <0xf00000 0x80000>; /* 512KB */
- read-only;
- lock;
- };
- partition@f80000 {
- label = "Image B (FSBL, PMU, ATF, U-Boot)";
- reg = <0xf80000 0xd00000>; /* 13MB */
- };
- partition@1c80000 {
- label = "ImgSel Image B Catch";
- reg = <0x1c80000 0x80000>; /* 512KB */
- read-only;
- lock;
- };
- partition@1d00000 {
- label = "Open_2";
- reg = <0x1d00000 0x100000>; /* 1MB */
- };
- partition@1e00000 {
- label = "Recovery Image";
- reg = <0x1e00000 0x200000>; /* 2MB */
- read-only;
- lock;
- };
- partition@2000000 {
- label = "Recovery Image Backup";
- reg = <0x2000000 0x200000>; /* 2MB */
- read-only;
- lock;
- };
- partition@2200000 {
- label = "U-Boot storage variables";
- reg = <0x2200000 0x20000>; /* 128KB */
- };
- partition@2220000 {
- label = "U-Boot storage variables backup";
- reg = <0x2220000 0x20000>; /* 128KB */
- };
- partition@2240000 {
- label = "SHA256";
- reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
- read-only;
- lock;
- };
- partition@2280000 {
- label = "Secure OS Storage";
- reg = <0x2280000 0x20000>; /* 128KB */
- };
- partition@22a0000 {
- label = "User";
- reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "Image Selector";
+ reg = <0x0 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@80000 {
+ label = "Image Selector Golden";
+ reg = <0x80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@100000 {
+ label = "Persistent Register";
+ reg = <0x100000 0x20000>; /* 128KB */
+ };
+ partition@120000 {
+ label = "Persistent Register Backup";
+ reg = <0x120000 0x20000>; /* 128KB */
+ };
+ partition@140000 {
+ label = "Open_1";
+ reg = <0x140000 0xc0000>; /* 768KB */
+ };
+ partition@200000 {
+ label = "Image A (FSBL, PMU, ATF, U-Boot)";
+ reg = <0x200000 0xd00000>; /* 13MB */
+ };
+ partition@f00000 {
+ label = "ImgSel Image A Catch";
+ reg = <0xf00000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@f80000 {
+ label = "Image B (FSBL, PMU, ATF, U-Boot)";
+ reg = <0xf80000 0xd00000>; /* 13MB */
+ };
+ partition@1c80000 {
+ label = "ImgSel Image B Catch";
+ reg = <0x1c80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@1d00000 {
+ label = "Open_2";
+ reg = <0x1d00000 0x100000>; /* 1MB */
+ };
+ partition@1e00000 {
+ label = "Recovery Image";
+ reg = <0x1e00000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition@2000000 {
+ label = "Recovery Image Backup";
+ reg = <0x2000000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition@2200000 {
+ label = "U-Boot storage variables";
+ reg = <0x2200000 0x20000>; /* 128KB */
+ };
+ partition@2220000 {
+ label = "U-Boot storage variables backup";
+ reg = <0x2220000 0x20000>; /* 128KB */
+ };
+ partition@2240000 {
+ label = "SHA256";
+ reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
+ read-only;
+ lock;
+ };
+ partition@2280000 {
+ label = "Secure OS Storage";
+ reg = <0x2280000 0x20000>; /* 128KB */
+ };
+ partition@22a0000 {
+ label = "User";
+ reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
index 2037686b9b45..1dc0414b33d6 100644
--- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
+++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
@@ -63,23 +63,27 @@
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <166000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "qspi-boot-bin";
- reg = <0x00000 0x60000>;
- };
- partition@60000 {
- label = "qspi-u-boot-itb";
- reg = <0x60000 0x100000>;
- };
- partition@160000 {
- label = "qspi-u-boot-env";
- reg = <0x160000 0x20000>;
- };
- partition@200000 {
- label = "qspi-rootfs";
- reg = <0x200000 0x1e00000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "qspi-boot-bin";
+ reg = <0x00000 0x60000>;
+ };
+ partition@60000 {
+ label = "qspi-u-boot-itb";
+ reg = <0x60000 0x100000>;
+ };
+ partition@160000 {
+ label = "qspi-u-boot-env";
+ reg = <0x160000 0x20000>;
+ };
+ partition@200000 {
+ label = "qspi-rootfs";
+ reg = <0x200000 0x1e00000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
index e9c6d249a8d1..94167770ed60 100644
--- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
+++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
@@ -88,15 +88,19 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <4>; /* maybe 4 here */
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
- partition@0 { /* for testing purpose */
- label = "qspi";
- reg = <0 0x4000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi";
+ reg = <0 0x4000000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts
index bd1e25571870..3e461d9c4d06 100644
--- a/arch/arm/dts/zynqmp-vpk120-revA.dts
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -88,15 +88,19 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
- partition@0 { /* for testing purpose */
- label = "qspi";
- reg = <0 0x4000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi";
+ reg = <0 0x4000000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts
index 9dcb90953712..34e5b6edab10 100644
--- a/arch/arm/dts/zynqmp-zc1232-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@@ -40,28 +40,32 @@
&qspi {
status = "okay";
flash@0 {
- compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */
- #address-cells = <1>;
- #size-cells = <1>;
+ compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts
index cf3e95832040..827143377b96 100644
--- a/arch/arm/dts/zynqmp-zc1254-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@@ -42,27 +42,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 32f317f3df40..33efdbf0e25e 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -357,28 +357,32 @@
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index e3d5cf972e83..13c304520a60 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -138,8 +138,6 @@
nand@0 {
reg = <0x0>;
- #address-cells = <0x2>;
- #size-cells = <0x1>;
nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-0";
@@ -147,35 +145,39 @@
nand-ecc-strength = <24>;
nand-on-flash-bbt;
- partition@0 { /* for testing purpose */
- label = "nand-fsbl-uboot";
- reg = <0x0 0x0 0x400000>;
- };
- partition@1 { /* for testing purpose */
- label = "nand-linux";
- reg = <0x0 0x400000 0x1400000>;
- };
- partition@2 { /* for testing purpose */
- label = "nand-device-tree";
- reg = <0x0 0x1800000 0x400000>;
- };
- partition@3 { /* for testing purpose */
- label = "nand-rootfs";
- reg = <0x0 0x1c00000 0x1400000>;
- };
- partition@4 { /* for testing purpose */
- label = "nand-bitstream";
- reg = <0x0 0x3000000 0x400000>;
- };
- partition@5 { /* for testing purpose */
- label = "nand-misc";
- reg = <0x0 0x3400000 0xfcc00000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "nand-fsbl-uboot";
+ reg = <0x0 0x0 0x400000>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand-linux";
+ reg = <0x0 0x400000 0x1400000>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand-device-tree";
+ reg = <0x0 0x1800000 0x400000>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand-rootfs";
+ reg = <0x0 0x1c00000 0x1400000>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand-bitstream";
+ reg = <0x0 0x3000000 0x400000>;
+ };
+ partition@5 { /* for testing purpose */
+ label = "nand-misc";
+ reg = <0x0 0x3400000 0xfcc00000>;
+ };
};
};
nand@1 {
reg = <0x1>;
- #address-cells = <0x2>;
- #size-cells = <0x1>;
nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-1";
@@ -183,29 +185,35 @@
nand-ecc-strength = <24>;
nand-on-flash-bbt;
- partition@0 { /* for testing purpose */
- label = "nand1-fsbl-uboot";
- reg = <0x0 0x0 0x400000>;
- };
- partition@1 { /* for testing purpose */
- label = "nand1-linux";
- reg = <0x0 0x400000 0x1400000>;
- };
- partition@2 { /* for testing purpose */
- label = "nand1-device-tree";
- reg = <0x0 0x1800000 0x400000>;
- };
- partition@3 { /* for testing purpose */
- label = "nand1-rootfs";
- reg = <0x0 0x1c00000 0x1400000>;
- };
- partition@4 { /* for testing purpose */
- label = "nand1-bitstream";
- reg = <0x0 0x3000000 0x400000>;
- };
- partition@5 { /* for testing purpose */
- label = "nand1-misc";
- reg = <0x0 0x3400000 0xfcc00000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "nand1-fsbl-uboot";
+ reg = <0x0 0x0 0x400000>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand1-linux";
+ reg = <0x0 0x400000 0x1400000>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand1-device-tree";
+ reg = <0x0 0x1800000 0x400000>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand1-rootfs";
+ reg = <0x0 0x1c00000 0x1400000>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand1-bitstream";
+ reg = <0x0 0x3000000 0x400000>;
+ };
+ partition@5 { /* for testing purpose */
+ label = "nand1-misc";
+ reg = <0x0 0x3400000 0xfcc00000>;
+ };
};
};
};
@@ -503,15 +511,18 @@
pinctrl-0 = <&pinctrl_spi0_default>;
spi0_flash0: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "sst,sst25wf080", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
- partition@0 {
- label = "spi0-data";
- reg = <0x0 0x100000>;
+ partition@0 {
+ label = "spi0-data";
+ reg = <0x0 0x100000>;
+ };
};
};
};
@@ -523,15 +534,18 @@
pinctrl-0 = <&pinctrl_spi1_default>;
spi1_flash0: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <20000000>;
reg = <0>;
-
- partition@0 {
- label = "spi1-data";
- reg = <0x0 0x84000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "spi1-data";
+ reg = <0x0 0x84000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index a8856c20f5b5..796669fc92c0 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -133,8 +133,6 @@
nand@0 {
reg = <0x0>;
- #address-cells = <0x2>;
- #size-cells = <0x1>;
nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-0";
@@ -142,65 +140,74 @@
nand-ecc-strength = <24>;
nand-on-flash-bbt;
- partition@0 { /* for testing purpose */
- label = "nand-fsbl-uboot";
- reg = <0x0 0x0 0x400000>;
- };
- partition@1 { /* for testing purpose */
- label = "nand-linux";
- reg = <0x0 0x400000 0x1400000>;
- };
- partition@2 { /* for testing purpose */
- label = "nand-device-tree";
- reg = <0x0 0x1800000 0x400000>;
- };
- partition@3 { /* for testing purpose */
- label = "nand-rootfs";
- reg = <0x0 0x1c00000 0x1400000>;
- };
- partition@4 { /* for testing purpose */
- label = "nand-bitstream";
- reg = <0x0 0x3000000 0x400000>;
- };
- partition@5 { /* for testing purpose */
- label = "nand-misc";
- reg = <0x0 0x3400000 0xfcc00000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "nand-fsbl-uboot";
+ reg = <0x0 0x0 0x400000>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand-linux";
+ reg = <0x0 0x400000 0x1400000>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand-device-tree";
+ reg = <0x0 0x1800000 0x400000>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand-rootfs";
+ reg = <0x0 0x1c00000 0x1400000>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand-bitstream";
+ reg = <0x0 0x3000000 0x400000>;
+ };
+ partition@5 { /* for testing purpose */
+ label = "nand-misc";
+ reg = <0x0 0x3400000 0xfcc00000>;
+ };
};
};
nand@1 {
reg = <0x1>;
- #address-cells = <0x2>;
- #size-cells = <0x1>;
nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-1";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
nand-on-flash-bbt;
-
- partition@0 { /* for testing purpose */
- label = "nand1-fsbl-uboot";
- reg = <0x0 0x0 0x400000>;
- };
- partition@1 { /* for testing purpose */
- label = "nand1-linux";
- reg = <0x0 0x400000 0x1400000>;
- };
- partition@2 { /* for testing purpose */
- label = "nand1-device-tree";
- reg = <0x0 0x1800000 0x400000>;
- };
- partition@3 { /* for testing purpose */
- label = "nand1-rootfs";
- reg = <0x0 0x1c00000 0x1400000>;
- };
- partition@4 { /* for testing purpose */
- label = "nand1-bitstream";
- reg = <0x0 0x3000000 0x400000>;
- };
- partition@5 { /* for testing purpose */
- label = "nand1-misc";
- reg = <0x0 0x3400000 0xfcc00000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "nand1-fsbl-uboot";
+ reg = <0x0 0x0 0x400000>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand1-linux";
+ reg = <0x0 0x400000 0x1400000>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand1-device-tree";
+ reg = <0x0 0x1800000 0x400000>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand1-rootfs";
+ reg = <0x0 0x1c00000 0x1400000>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand1-bitstream";
+ reg = <0x0 0x3000000 0x400000>;
+ };
+ partition@5 { /* for testing purpose */
+ label = "nand1-misc";
+ reg = <0x0 0x3400000 0xfcc00000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 3b03b39e456a..cd80aed9a388 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -174,27 +174,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 3d71742fcbee..9590dd1cd92a 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -986,28 +986,32 @@
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index b4e62bf6bb61..3fe7cb410bcf 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -452,27 +452,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index f7a91402a097..21ce50e1da93 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -464,27 +464,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 5eb5f77220d6..0ac1472c55dd 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -980,28 +980,32 @@
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 72d331a740fa..7894daeca943 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -803,28 +803,32 @@
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index cc9f5b160254..b9d51fadc2ab 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -46,27 +46,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index f78da0362800..f26d9843243b 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -73,27 +73,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5e0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
};
};
};
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 5/9] arm64: zynqmp: Add CMA reserved-memory for runtime FPGA loading
2026-06-09 7:48 [PATCH 0/9] arm64: zynqmp: DT updates Michal Simek
` (3 preceding siblings ...)
2026-06-09 7:48 ` [PATCH 4/9] arm64: zynqmp: Use fixed-partitions for MTD Michal Simek
@ 2026-06-09 7:48 ` Michal Simek
2026-06-09 7:48 ` [PATCH 6/9] arm64: zynqmp: add USB hub supply regulators Michal Simek
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2026-06-09 7:48 UTC (permalink / raw)
To: u-boot, git
Cc: Nithish Kumar Naroju, Radhey Shyam Pandey, Rohit Visavalia,
Tom Rini
Add CMA (Contiguous Memory Allocator) reserved-memory regions to all
Xilinx arm64 board device trees to support runtime FPGA programming.
The CMA pool uses dynamic allocation constrained to the low 2 GB DDR region
via alloc-ranges so that the kernel places it within the 32-bit addressable
space.
CMA sizes are chosen per silicon family to accommodate the maximum PL
bitstream/PDI size:
- Kria K24 SOM: 64 MB
- ZynqMP boards: 128 MB
For Kria K24 SOM the CMA inherited from K26 is overridden to 64 MB.
For Kria SOMs, the CMA node is added to the SOM DTS only, not to
carrier board overlays.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/zynqmp-sm-k24-revA.dts | 7 ++++++-
arch/arm/dts/zynqmp-sm-k26-revA.dts | 11 ++++++++++-
arch/arm/dts/zynqmp-zc1232-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zc1254-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu100-revC.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu102-revA.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu104-revA.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu104-revC.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu106-revA.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu111-revA.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu1275-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu1275-revB.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu1285-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu208-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu216-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu670-revA.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu670-revB.dts | 17 ++++++++++++++++-
22 files changed, 326 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts
index 653bd9362264..34ee6af801de 100644
--- a/arch/arm/dts/zynqmp-sm-k24-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP SM-K24 RevA
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2022, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022-2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -21,3 +21,8 @@
reg = <0 0 0 0x80000000>;
};
};
+
+&cma {
+ size = <0x0 0x4000000>;
+ alignment = <0x0 0x4000000>;
+};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 0abec77b3f3a..c7fe253244f6 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -61,6 +61,15 @@
reg = <0x0 0x7ff00000 0x0 0x100000>;
no-map;
};
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
};
gpio-keys {
diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts
index 34e5b6edab10..f0e2a0b4588f 100644
--- a/arch/arm/dts/zynqmp-zc1232-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@@ -31,6 +31,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&dcc {
diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts
index 827143377b96..e92caefd3aa2 100644
--- a/arch/arm/dts/zynqmp-zc1254-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@@ -32,6 +32,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&dcc {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 33efdbf0e25e..2897c423f82e 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -41,6 +41,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
clock_si5338_0: clk27 { /* u55 SI5338-GM */
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 13c304520a60..0b1185d862cd 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -39,6 +39,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&can0 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index 796669fc92c0..bfcc92cedfad 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -39,6 +39,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
clock_si5338_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index cd80aed9a388..9b59952993f1 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -38,6 +38,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&can0 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 53aa3dca1dca..722b2e833b44 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -37,6 +37,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&fpd_dma_chan1 {
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 4ec8a400494e..62f94da334db 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU100 revC
*
* (C) Copyright 2016 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Nathalie Chan King Choy
@@ -47,6 +47,21 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 9590dd1cd92a..a0ef866a259a 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU102 RevA
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -45,6 +45,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 3fe7cb410bcf..4479ff735145 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
clock_8t49n287_5: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 21ce50e1da93..0caedc40a519 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
ina226 {
compatible = "iio-hwmon";
io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 0ac1472c55dd..c0bc46faee4e 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU106
*
* (C) Copyright 2016 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -45,6 +45,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 7894daeca943..f38edd6145f5 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU111
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -45,6 +45,21 @@
/* Another 4GB connected to PL */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index b9d51fadc2ab..1a49ae3ba4e4 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -32,6 +32,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&dcc {
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index f26d9843243b..1b6f7a605d6f 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -35,6 +35,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&dcc {
diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts
index 86a3217f9ab6..b2d71f0f4556 100644
--- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@@ -36,6 +36,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&dcc {
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 70b1e81e304c..3c3c94dcadfc 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index bc0ca24ff050..b0f0a74f711e 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts
index 1215babe2146..c5b70972ef52 100644
--- a/arch/arm/dts/zynqmp-zcu670-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU670 (67DR)
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -46,6 +46,21 @@
/* Another 4GB connected to PL */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts
index e91f280e4576..cd96a7a0d136 100644
--- a/arch/arm/dts/zynqmp-zcu670-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revB.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU670 (67DR) revB
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -46,6 +46,21 @@
/* Another 4GB connected to PL */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 6/9] arm64: zynqmp: add USB hub supply regulators
2026-06-09 7:48 [PATCH 0/9] arm64: zynqmp: DT updates Michal Simek
` (4 preceding siblings ...)
2026-06-09 7:48 ` [PATCH 5/9] arm64: zynqmp: Add CMA reserved-memory for runtime FPGA loading Michal Simek
@ 2026-06-09 7:48 ` Michal Simek
2026-06-09 7:48 ` [PATCH 7/9] arm64: zynqmp: dts: Fix file descriptions to match actual filenames Michal Simek
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2026-06-09 7:48 UTC (permalink / raw)
To: u-boot, git
Cc: Shaikh Mohammed Suhan, Radhey Shyam Pandey, Nithish Kumar Naroju,
Rob Herring (Arm), Rohit Visavalia, Tom Rini
From: Shaikh Mohammed Suhan <suhan.sm@amd.com>
Add fixed supply regulators for the onboard USB hub (USB2744) used on
Kria platforms.
The USB hub requires two always-on power rails:
- vdd: 3.3V main supply
- vdd2: auxiliary supply
Model these rails as fixed regulators and reference them from the hub
node to accurately describe the hardware.
Signed-off-by: Shaikh Mohammed Suhan <suhan.sm@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 20 ++++++++++++++++++++
arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 22 ++++++++++++++++++++++
arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 22 ++++++++++++++++++++++
arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 20 ++++++++++++++++++++
arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 20 ++++++++++++++++++++
5 files changed, 104 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
index 021bf8ac26e6..02b9d82eb7c7 100644
--- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -50,6 +50,24 @@
gpio-controller;
gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
};
+
+ vdd_usb_hub: regulator-vdd-usb-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usb_hub";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd2_usb_hub: regulator-vdd2-usb-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd2_usb_hub";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&can0 {
@@ -124,6 +142,8 @@
peer-hub = <&hub_3_0>;
i2c-bus = <&hub>;
reset-gpios = <&slg_delay 0 10000 10000>;
+ vdd-supply = <&vdd_usb_hub>;
+ vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
index 048aeb1e7654..47f0fb5f74f1 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
@@ -85,6 +85,24 @@
gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>,
<&slg7xl45106 4 GPIO_ACTIVE_LOW>;
};
+
+ vdd_usb_hub: regulator-vdd-usb-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usb_hub";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd2_usb_hub: regulator-vdd2-usb-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd2_usb_hub";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -196,6 +214,8 @@
peer-hub = <&hub_3_0>;
i2c-bus = <&hub_1>;
reset-gpios = <&slg_delay 0 10000 10000>;
+ vdd-supply = <&vdd_usb_hub>;
+ vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
@@ -233,6 +253,8 @@
peer-hub = <&hub1_3_0>;
i2c-bus = <&hub_2>;
reset-gpios = <&slg_delay 1 10000 10000>;
+ vdd-supply = <&vdd_usb_hub>;
+ vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index 2eef6ba7df75..b3c75f67bbd6 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -86,6 +86,24 @@
gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>,
<&slg7xl45106 4 GPIO_ACTIVE_LOW>;
};
+
+ vdd_usb_hub: regulator-vdd-usb-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usb_hub";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd2_usb_hub: regulator-vdd2-usb-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd2_usb_hub";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -197,6 +215,8 @@
peer-hub = <&hub_3_0>;
i2c-bus = <&hub_1>;
reset-gpios = <&slg_delay 0 10000 10000>;
+ vdd-supply = <&vdd_usb_hub>;
+ vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
@@ -234,6 +254,8 @@
peer-hub = <&hub1_3_0>;
i2c-bus = <&hub_2>;
reset-gpios = <&slg_delay 1 10000 10000>;
+ vdd-supply = <&vdd_usb_hub>;
+ vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
index ea947cd2dc02..3c551f303150 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
@@ -85,6 +85,24 @@
gpio-controller;
gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
+
+ vdd_usb_hub: regulator-vdd-usb-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usb_hub";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd2_usb_hub: regulator-vdd2-usb-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd2_usb_hub";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
@@ -169,6 +187,8 @@
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&slg_delay 0 10000 10000>;
+ vdd-supply = <&vdd_usb_hub>;
+ vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
index ea7b9253468e..a60bd7b7bdb2 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
@@ -81,6 +81,24 @@
gpio-controller;
gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
+
+ vdd_usb_hub: regulator-vdd-usb-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usb_hub";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd2_usb_hub: regulator-vdd2-usb-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd2_usb_hub";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
@@ -156,6 +174,8 @@
peer-hub = <&hub_3_0>;
i2c-bus = <&hub>;
reset-gpios = <&slg_delay 0 10000 10000>;
+ vdd-supply = <&vdd_usb_hub>;
+ vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 7/9] arm64: zynqmp: dts: Fix file descriptions to match actual filenames
2026-06-09 7:48 [PATCH 0/9] arm64: zynqmp: DT updates Michal Simek
` (5 preceding siblings ...)
2026-06-09 7:48 ` [PATCH 6/9] arm64: zynqmp: add USB hub supply regulators Michal Simek
@ 2026-06-09 7:48 ` Michal Simek
2026-06-09 7:48 ` [PATCH 8/9] arm64: dts: xilinx: Drop "label" property on dlg, slg7xl45106 Michal Simek
2026-06-09 7:48 ` [PATCH 9/9] arm64: zynqmp: Sync compatible string format Michal Simek
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2026-06-09 7:48 UTC (permalink / raw)
To: u-boot, git
Cc: Padmarao Begari, Radhey Shyam Pandey, Shaikh Mohammed Suhan,
Tom Rini
Fix descriptions that don't match their filenames:
- zynqmp-sc-vpk180-revB.dtso: described as revA instead of revB
- zynqmp-sck-kv-g-revB.dtso: described as revA instead of revB
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/zynqmp-sc-vpk180-revB.dtso | 2 +-
arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
index 74e1c5c6dc94..6a5ada34ed71 100644
--- a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * dts file for Xilinx ZynqMP VPK180 revA
+ * dts file for Xilinx ZynqMP VPK180 revB
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
index a60bd7b7bdb2..0fa5a990adc8 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * dts file for KV260 revA Carrier Card
+ * dts file for KV260 revB Carrier Card
*
* (C) Copyright 2020 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 8/9] arm64: dts: xilinx: Drop "label" property on dlg, slg7xl45106
2026-06-09 7:48 [PATCH 0/9] arm64: zynqmp: DT updates Michal Simek
` (6 preceding siblings ...)
2026-06-09 7:48 ` [PATCH 7/9] arm64: zynqmp: dts: Fix file descriptions to match actual filenames Michal Simek
@ 2026-06-09 7:48 ` Michal Simek
2026-06-09 7:48 ` [PATCH 9/9] arm64: zynqmp: Sync compatible string format Michal Simek
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2026-06-09 7:48 UTC (permalink / raw)
To: u-boot, git
Cc: Rob Herring (Arm), Nithish Kumar Naroju, Radhey Shyam Pandey,
Rohit Visavalia, Shaikh Mohammed Suhan, Tom Rini
From: "Rob Herring (Arm)" <robh@kernel.org>
The "label" property is not documented for the dlg,slg7xl45106. Nor is
it common to use for GPIO controllers. So drop it.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 1 -
arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 1 -
arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 1 -
3 files changed, 3 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
index 02b9d82eb7c7..a32073fa0404 100644
--- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -94,7 +94,6 @@
slg7xl45106: gpio@11 { /* u13 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
- label = "resetchip";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "",
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
index 47f0fb5f74f1..2bc28b7baf85 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
@@ -123,7 +123,6 @@
slg7xl45106: gpio@11 { /* u19 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
- label = "resetchip";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index b3c75f67bbd6..f1114a35aaef 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -124,7 +124,6 @@
slg7xl45106: gpio@11 { /* u19 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
- label = "resetchip";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 9/9] arm64: zynqmp: Sync compatible string format
2026-06-09 7:48 [PATCH 0/9] arm64: zynqmp: DT updates Michal Simek
` (7 preceding siblings ...)
2026-06-09 7:48 ` [PATCH 8/9] arm64: dts: xilinx: Drop "label" property on dlg, slg7xl45106 Michal Simek
@ 2026-06-09 7:48 ` Michal Simek
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2026-06-09 7:48 UTC (permalink / raw)
To: u-boot, git; +Cc: Padmarao Begari, Tom Rini
There is no reason to have non zynqmp-sc compatible string for overlays
which can be applied only with SCs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/zynqmp-sc-vek280-revA.dtso | 5 ++---
arch/arm/dts/zynqmp-sc-vek280-revB.dtso | 5 ++---
arch/arm/dts/zynqmp-sc-vhk158-revA.dtso | 5 ++---
arch/arm/dts/zynqmp-sc-vpk120-revB.dtso | 5 ++---
arch/arm/dts/zynqmp-sc-vpk180-revA.dtso | 5 ++---
arch/arm/dts/zynqmp-sc-vpk180-revB.dtso | 5 ++---
6 files changed, 12 insertions(+), 18 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
index e94b784e8e1f..7212ee9df86b 100644
--- a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP VEK280 revA
*
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -13,8 +13,7 @@
/plugin/;
&{/} {
- compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA",
- "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+ compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp";
vc7_xin: vc7-xin {
compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
index a3983f330d07..a57e9b50b20c 100644
--- a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
+++ b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP VEK280 revB
*
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -10,6 +10,5 @@
#include "zynqmp-sc-vek280-revA.dtso"
&{/} {
- compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB",
- "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+ compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp";
};
diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
index fd25731b0b43..2fe35596143b 100644
--- a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP VHK158 revA
*
* (C) Copyright 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -14,8 +14,7 @@
/plugin/;
&{/} {
- compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA",
- "xlnx,zynqmp-vhk158", "xlnx,zynqmp";
+ compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-sc-vhk158", "xlnx,zynqmp";
vc7_xin: vc7-xin {
compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
index 29b3a73fde01..ae0691c01271 100644
--- a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP VPK120 revB
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -14,8 +14,7 @@
/plugin/;
&{/} {
- compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB",
- "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
+ compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-sc-vpk120", "xlnx,zynqmp";
};
&i2c0 {
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
index 10466ce99de6..9b6534f6383c 100644
--- a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP VPK180 revA
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -14,8 +14,7 @@
/plugin/;
&{/} {
- compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA",
- "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+ compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp";
vc7_xin: vc7-xin {
compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
index 6a5ada34ed71..941d26c025a8 100644
--- a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP VPK180 revB
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -14,8 +14,7 @@
/plugin/;
&{/} {
- compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB",
- "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+ compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp";
vc7_xin: vc7-xin {
compatible = "fixed-clock";
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2026-06-09 7:50 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-06-09 7:48 [PATCH 0/9] arm64: zynqmp: DT updates Michal Simek
2026-06-09 7:48 ` [PATCH 1/9] arm64: zynqmp-dlc21-revA: Update GPIO line names mapping Michal Simek
2026-06-09 7:48 ` [PATCH 2/9] arm64: zynqmp-dlc21-revA: add mac nvmem cell for gem0 Michal Simek
2026-06-09 7:48 ` [PATCH 3/9] arm64: zynqmp: Drop incorrect #phy-cells from ethernet-phy nodes Michal Simek
2026-06-09 7:48 ` [PATCH 4/9] arm64: zynqmp: Use fixed-partitions for MTD Michal Simek
2026-06-09 7:48 ` [PATCH 5/9] arm64: zynqmp: Add CMA reserved-memory for runtime FPGA loading Michal Simek
2026-06-09 7:48 ` [PATCH 6/9] arm64: zynqmp: add USB hub supply regulators Michal Simek
2026-06-09 7:48 ` [PATCH 7/9] arm64: zynqmp: dts: Fix file descriptions to match actual filenames Michal Simek
2026-06-09 7:48 ` [PATCH 8/9] arm64: dts: xilinx: Drop "label" property on dlg, slg7xl45106 Michal Simek
2026-06-09 7:48 ` [PATCH 9/9] arm64: zynqmp: Sync compatible string format Michal Simek
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.