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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3142a1dde81sm66281257eec.21.2026.07.20.10.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 10:41:11 -0700 (PDT) From: Matheus Tavares Bernardino To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, marco.liebel@oss.qualcomm.com, philmd@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng Subject: [PATCH v3 00/13] hexagon: add semihosting support Date: Mon, 20 Jul 2026 10:40:56 -0700 Message-Id: X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIwMDE5MyBTYWx0ZWRfX5s6xNWntFObC QK8FsUN9Gww1hCiAyxK5QM5NNqjMl8qutPNFM8p1lnfeW+lk0pGKmdPmCmXrkXlt7Jmov7yElGJ w4k+byfP+2nKDBp306478Wmh3m9KXsU= X-Proofpoint-ORIG-GUID: t2HMUboyYV4KsN6gpbuiMM2V2Zvwyjqx X-Authority-Analysis: v=2.4 cv=DMS/JSNb c=1 sm=1 tr=0 ts=6a5e5db9 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=2klBbvr5IC3WPyomHCoA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: t2HMUboyYV4KsN6gpbuiMM2V2Zvwyjqx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIwMDE5MyBTYWx0ZWRfX46Tp4GkdA0bb zQNE4wtZaENH+XUbCBoFYKNDUcVskNMT2mzDF4pn8UFS5m/pqpY22V8nKJC30lYwWAr4wmOqAAC JaUk5mShO/ORwY5C7Alhw9HEO2qAleWQZFT8pNGckpauks8PX6deMHarePgFKnJq9atrFRawAKf MuninV+656F80TyOqioaTlHt8RjMpk5uX637XmVMJtuEuOWm2Sh79+umaonNvETrCfmk9RJUIMY oAIieFEq9bwC8fAXXxziq1ER/NXdpfYCfCqXvToSsh574iN6KsukE0/+/62WBl4WHhgYqMeQov2 Ej8bOs6iZuYbzUtFBLTCh2uw/kNbYVrOU86s+hiTIQrrmhorbzVgydoyyv1CW0r2dEmVFuDrt+n jjmcCRjuf+7TarVH2QeSKtOq54PsJ/p8+Sc4ai1pwEjJKiP308SB+4YfOE4oZTePMC1PT3xWxCd X4u5pO7VsS5DHV3u3aA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_04,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 priorityscore=1501 spamscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607200193 Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series adds semihosting support to hexagon system emulation, together with functional tests for the added operations. The Hexagon semihosting spec can be found at: https://docs.qualcomm.com/doc/80-N2040-101_102648/topic/semihosting-specification.html v1: https://lore.kernel.org/qemu-devel/cover.1783973054.git.matheus.bernardino@oss.qualcomm.com/ v2: https://lore.kernel.org/qemu-devel/3cd3a419-ee2c-4d7a-9396-60eab8d26908@oss.qualcomm.com/T/#m9e966877cda81c5661838fedadf4e69bd912cbb5 Changes in v3: - Reworded semihosting section at Hexagon docs - Rebased, added Reviewed-by's, dropped already merged patch Changes in v2: - Added patch 1, a fix for an existing bug that appeared with the new test semantics from the last patch. - Patch 3: s/hexagon_touch_memory/hexagon_peek_memory_range/ - Patch 7: * Add semihosting spec link to docs * Fixed HEX_SYS_EXCEPTION - Patch 10: * Moved tables to static definition * Fixed compilation for Windows - Dropped patch 11 (OPEN/READ/CLOSE_DIR support): for now we don't have dirent semantics for Windows, so leave these ops to a followup series. - Patch 14: * Update test version * Don't change directory * Don't use os.path, use scratch_file Brian Cain (4): semihosting: add APIs for chardev-aware guest fd routing target/hexagon: Add an errno mapping python/machine: support routing semihosting output to the test console tests/functional: Add hexagon semihosting systests Matheus Tavares Bernardino (9): target/hexagon: fix improper assign of cause code to exception index target/hexagon: fix PC advancement for non-COF TB terminators target/hexagon: add aux functions for guest mem load/store hexagon: cpu_helper: add reg reading/writing helpers semihosting: add callback to set error target/hexagon: add semihosting support semihosting: add ftruncate helper (to be used for hexagon) target/hexagon: add main arch-specific semihosting operations target/hexagon: add COREDUMP semihosting operation docs/system/target-hexagon.rst | 8 +- configs/targets/hexagon-softmmu.mak | 2 + include/semihosting/common-semi.h | 2 + include/semihosting/console.h | 9 + include/semihosting/guestfd.h | 9 + include/semihosting/syscalls.h | 2 + target/hexagon/cpu_helper.h | 24 + target/hexagon/internal.h | 1 + hw/hexagon/hexagon_dsp.c | 2 + semihosting/arm-compat-semi.c | 3 +- semihosting/console.c | 5 + semihosting/guestfd.c | 8 + semihosting/syscalls.c | 29 + target/arm/common-semi-target.c | 4 + target/hexagon/common-semi-target.c | 51 ++ target/hexagon/cpu.c | 5 +- target/hexagon/cpu_helper.c | 173 ++++++ target/hexagon/hexswi.c | 657 +++++++++++++++++++++- target/hexagon/op_helper.c | 18 +- target/hexagon/translate.c | 17 +- target/riscv/common-semi-target.c | 4 + hw/hexagon/Kconfig | 1 + python/qemu/machine/machine.py | 10 +- qemu-options.hx | 8 +- target/hexagon/meson.build | 3 + tests/functional/hexagon/meson.build | 5 + tests/functional/hexagon/test_systests.py | 110 ++++ 27 files changed, 1135 insertions(+), 35 deletions(-) create mode 100644 target/hexagon/common-semi-target.c create mode 100755 tests/functional/hexagon/test_systests.py Range-diff against v2: 1: aaac9492e5a ! 1: 4f4ec84cb85 target/hexagon: fix improper assign of cause code to exception index @@ Commit message gen_exception(), which treats its argument as an event index and stores it directly in cs->exception_index. + Reviewed-by: Pierrick Bouvier Signed-off-by: Matheus Tavares Bernardino ## target/hexagon/cpu.c ## 2: 2f5247200ec < -: ----------- target/hexagon: fix get_phys_addr_debug with in-page offset 3: 2cac81d1782 = 2: ab16d424acd target/hexagon: fix PC advancement for non-COF TB terminators 4: b0f794c467a ! 3: db1ec7611b7 target/hexagon: add aux functions for guest mem load/store @@ Commit message Will be used for semihosting. - Signed-off-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier + Signed-off-by: Matheus Tavares Bernardino ## target/hexagon/cpu_helper.h ## @@ 5: 5b16ff40a6e = 4: b02e7a60814 hexagon: cpu_helper: add reg reading/writing helpers 6: 90074658cf5 = 5: c540d8251f2 semihosting: add APIs for chardev-aware guest fd routing 7: a08d1e274e7 = 6: a130a83d7a1 semihosting: add callback to set error 8: 5c5c06f35f7 ! 7: 0c46c3d9cf8 target/hexagon: add semihosting support @@ Commit message CONFIG_ARM_COMPATIBLE_SEMIHOSTING and routing trap0 to the semihosting handler. - Signed-off-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier + Signed-off-by: Matheus Tavares Bernardino ## docs/system/target-hexagon.rst ## @@ docs/system/target-hexagon.rst: Semihosting @@ docs/system/target-hexagon.rst: Semihosting +guest software can access the host console and filesystem. Read the +`Hexagon Semihosting Specification +`__ -+for details. Semihosting is enabled on qemu-system-hexagon machines by default, -+and it can be configured through ``-semihosting-config``. ++for details. Semihosting is enabled by default on hexagon-sim-compatible ++machines. This can be further configured through ``-semihosting-config``. Hexagon Features ================ 9: 7399327e99b = 8: 6bff530121c semihosting: add ftruncate helper (to be used for hexagon) 10: b66476c599c ! 9: 96776c988e4 target/hexagon: add main arch-specific semihosting operations @@ Commit message perform file I/O when running on qemu-system-hexagon. Signed-off-by: Brian Cain + Reviewed-by: Pierrick Bouvier Signed-off-by: Matheus Tavares Bernardino ## include/semihosting/common-semi.h ## 11: 7fd1831acb4 ! 10: 9ac447d6831 target/hexagon: add COREDUMP semihosting operation @@ Commit message Implement the handler to decode the SSR cause field and print the full register file, matching hexagon-sim behavior. - Signed-off-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier + Signed-off-by: Matheus Tavares Bernardino ## target/hexagon/internal.h ## @@ target/hexagon/internal.h: int hexagon_hvx_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n); 12: 24731ad7a27 = 11: bf030fc808d target/hexagon: Add an errno mapping 13: c16ea7a7e6c = 12: 6d1f197c4ac python/machine: support routing semihosting output to the test console 14: 87a6d2559c3 ! 13: 4299b53256d tests/functional: Add hexagon semihosting systests @@ Commit message Reviewed-by: Pierrick Bouvier Signed-off-by: Matheus Tavares Bernardino - ## tests/functional/hexagon/meson.build (new) ## + ## tests/functional/hexagon/meson.build ## @@ -+# SPDX-License-Identifier: GPL-2.0-or-later + + tests_hexagon_system_thorough = [ + 'arch_tests', ++ 'systests', + ] + +test_hexagon_timeouts = { + 'systests': 180, +} -+ -+tests_hexagon_system_thorough = [ -+ 'systests', -+] ## tests/functional/hexagon/test_systests.py (new) ## @@ @@ tests/functional/hexagon/test_systests.py (new) + +if __name__ == "__main__": + QemuSystemTest.main() - - ## tests/functional/meson.build ## -@@ tests/functional/meson.build: subdir('aarch64') - subdir('alpha') - subdir('arm') - subdir('avr') -+subdir('hexagon') - subdir('hppa') - subdir('i386') - subdir('loongarch64') -- 2.37.2