From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3591B3E92A5 for ; Tue, 21 Jul 2026 08:08:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621326; cv=none; b=aguakUGVI9JTzj5FFjzJuwd4FCQoAXsGSUl4KC+eL7AWplIHFeF216H1TnQa869e23jnhd4EScTQzBHn4eNL6f3l3MAUsDhFoMBb3CCHHjppeoN2hpBRtqRfmg2iQHddsHCZ+DQ5/LxzQ968ZPuQaxW0dxip4M3keWz0egNGq+k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621326; c=relaxed/simple; bh=DsinLfb+fX0R7lm2VHaxmf+nQkZjBXS8n8hn+7ukvVI=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=ZDvO9iQ3siD3Lcjes8WCeXUBgPZ9D/DOfQBs0pHOvqi9dAQ056Doyieb4LSYIfZiY7aTRZ0RagtHXJlPXe9WX/MijG8HM/JNctyMIrKsa08ToQ1UCHx65MviGfcwzrOLJVs/cXbRDsmqhVz8n6jo5bBkHVuS3KxGPEH9l6Q8oW0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AT2FRikf; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AT2FRikf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2CBCB1F000E9; Tue, 21 Jul 2026 08:08:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784621324; bh=tlB6pnFFhcvjlCIZP0fc7YRv5VlYsEdmPm8RgcTFlsc=; h=From:To:Cc:Subject:Date; b=AT2FRikfLT6AYd2CV0Brg+Byn2tzeIOj0X2GZZD/YiX1AHbMKDZUR8JTjG8QenDSG DoLyhZ98VoQXqog4yDG6OArpETarPdlRleNrNTvnVO+6wiZFyhc5yYzWWIDLm/y4K8 jLJWZIwdh2o5BNPSzUXJJApZOkYfofouWoNtJK82eijlNafYLIiF4z4ToavURYtzwt r74bhocW9BsSXiVXIpMWGGr6AjzHPG+k1dmxu6PaSjTfakvoTnq+Js+nFWrF7bEYQI r34C+K/UC2GutIoZ7QuDhE3ys1jo1XWZhV6qniHpb84nmuHjz3HEzZ4Kf28EoZgd9Q DJEt8VkCWo2jw== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" , Thomas Gleixner Subject: [PATCH v3 0/3] Support additional AMD EILVT registers Date: Tue, 21 Jul 2026 13:33:34 +0530 Message-ID: X-Mailer: git-send-email 2.54.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for additional APIC EILVT registers being introduced in future AMD processors: https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB) This is mostly a re-send of v2, except for a small change in patch 2/3 where I have dropped the KVM export for apic_eilvt_count - it can be introduced in the series adding the KVM user for the same. v2: http://lore.kernel.org/r/cover.1778594390.git.naveen@kernel.org - Naveen Naveen N Rao (AMD) (3): perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 x86/apic: Introduce a variable to track the number of EILVT registers x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 2 +- arch/x86/events/amd/ibs.c | 4 ++-- arch/x86/kernel/apic/apic.c | 18 ++++++++++++++++-- 4 files changed, 21 insertions(+), 5 deletions(-) base-commit: e9dac177a4ea335a3f035f81405088e17947f258 -- 2.54.0