From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 311E935BDAA for ; Thu, 23 Jul 2026 05:47:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785661; cv=none; b=tFcmU2vWncyUiE8xvvqBAe8FJ9WWNLDnKDz24GzZXxdAp9kPsqqf8W8/1DPJpk/xMf4L9NXLMkG3u360sKjvquXBIHq7NL1MvJBa0E9jCQCSGQE8+Ie8yOcABSG1FdQYsUeKDOQIY/MUuKVJhp/OKBDMVJhABL86kCd1DSAWU2A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785661; c=relaxed/simple; bh=j26VgnWPARLvI2cULJnsoOF8GJKBGVeFXyswnCI2oTY=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=LXAIpcDczCg83Z/L1ctF38YhroSQ2JkcNu212gbpowZKu1wzifxSdd+8GSdq0NdBtMpWx0rbeS5sTRZAVnqk5cj84Qrt+ra8FnPNFxEhG9rhpfKChQjGDAZVGHUY9JIIssK7+xcWRSc8FwCSbywEkZqArRVr3hknyd9LPatmNEA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ayEKAJZy; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ayEKAJZy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 43EAD1F000E9; Thu, 23 Jul 2026 05:47:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784785660; bh=CIAh7fYUrCkUMQW4RAq5Ob9KSfotb5siHkomAGIxHx8=; h=From:To:Cc:Subject:Date; b=ayEKAJZyDuK1WdXcKv4wqziyLNDq8JfiaP+romQEoqkOEqqFVYKbrfm6wBi9iNHbi wq1cf5VyrfcP69ngaDNPNUtGEyuRhonDIi9w7bJmgoVGdeVt1TmkjTs+A9aFAvnPGt LV5gUZPy28l3g6ilM6XAcaZZ3k0ASCAjgGjHBE/lzGDI3onejfYSUnapPYTpGe/jSB vGLjAh9H5YL/g91rBnihrsnaletoxZvTwvmzpIbI9t7RCHRwy/j59m5Dag8ITDOyuU cHFiqJTgtwLeegmAvnMIXFbZmc9kArWUlS3FTG2czDL086tr5ri6CRAf00NtGH8K0u mvRJfWlh2dfRQ== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Thomas Gleixner , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" Subject: [PATCH v4 0/3] Support additional AMD EILVT registers Date: Thu, 23 Jul 2026 11:14:05 +0530 Message-ID: X-Mailer: git-send-email 2.54.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for additional APIC EILVT registers being introduced in future AMD processors: https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB) Since v3 (http://lore.kernel.org/r/cover.1784619898.git.naveen@kernel.org): - Move apic_eilvt_count into 'struct apic' (Thomas Gleixner) - Rename apic_eilvt_count to eilvt_regs_count to more accurately reflect its purpose. - Naveen Naveen N Rao (AMD) (3): perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 x86/apic: Introduce a variable to track the number of EILVT registers x86/apic: Drop APIC_EILVT_NR_MAX arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 2 +- arch/x86/events/amd/ibs.c | 4 ++-- arch/x86/kernel/apic/apic.c | 17 +++++++++++++++-- 4 files changed, 20 insertions(+), 5 deletions(-) base-commit: 385a91beefc86cb6b7f05b2c3a59b2b82c38c92e -- 2.54.0