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- named enum slots for the PHY/HRS config tables, so reordering or inserting an entry cannot silently reprogram the wrong register (no functional change); - program the PHY control register (0x2080) per speed mode, with a per-mode / per-board device-tree override; - add the SDR104 (emmc-hs200) and DDR50 (emmc-ddr) PHY timing for the Agilex5 SoCDK, 013B and modular boards and advertise the matching sd-uhs-* / mmc-ddr-1_8v capabilities. Dependencies ------------ The driver patches (1-3) apply on top of, and depend on, the fixes series (series=519635): "mmc: sdhci-cadence6: fix PHY programming reliability" The HRS05 posted-write flush and the post-adjustment settle delay from that series are required for reliable higher-speed operation. The device-tree patch (4) additionally depends on two Agilex5 board patches still under review, as it extends the .dts/.dtsi files they add: "arm: dts: socfpga: Add MDK support with external GPIO expander" - Tanmay Kathpalia (series=16401) "arm: dts: socfpga: Add Agilex5 E-Series 013B SoCDK variant" - Dinesh Maniyam (series=32177) Tze Yee Ng (4): mmc: sdhci-cadence6: use const PHY config tables with per-call overrides mmc: sdhci-cadence6: name PHY and controller config table slots mmc: sdhci-cadence6: configure PHY control register per speed mode arm: dts: socfpga: agilex5: add SD/eMMC UHS PHY timing .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 13 ++ .../socfpga_agilex5_socdk_013b-u-boot.dtsi | 24 +++- arch/arm/dts/socfpga_agilex5_socdk_013b.dts | 4 +- arch/arm/dts/socfpga_agilex5_socdk_emmc.dts | 13 ++ .../arm/dts/socfpga_agilex5_socdk_modular.dts | 20 +++ drivers/mmc/sdhci-cadence6.c | 136 ++++++++++++------ 6 files changed, 166 insertions(+), 44 deletions(-) -- 2.43.7