[PATCH 0/7] phy: spacemit: k1: fix the PCIe and combo PHY driver

[Dave Klotz <DaveWK225@protonmail.com>]

Fixes for the K1 PCIe/combo PHY driver from "phy: spacemit: add K1
PCIe/USB3 combo PHY driver", bringing it in line with the Linux driver:

- enable refclk and take the PHY out of reset at probe, using the clock
  and reset the binding names, instead of fetching them unused;
- calibrate the termination values the way Linux does, without starting
  port A's PLL in PCIe mode, and put port A back as it was afterwards;
- clear the termination fields before writing them, set EN_RTERM, set
  CLKSEL on every lane, and update the PLL control registers with
  read-modify-write instead of overwriting them;
- add a power_on op that brings the combo PHY up in USB 3 mode (select,
  test control, timer adjust, SSC, PLL lock wait). Switching the select
  bit alone leaves the PLL unlocked and the xHCI reset never completes.

Tested on an OrangePi RV2: NVMe on PCIe port B (link up, EFI boot from
the drive), an empty port C reporting no link, and a USB 3 stick behind
the on-board hub enumerating at 5 Gb/s through the combo PHY with a
DWC3 glue driver I will post separately. Not tested: a device on
port C, or USB 3 on other K1 boards.

Dave Klotz (7):
  phy: spacemit: k1: enable refclk and deassert the PHY reset at probe
  phy: spacemit: k1: don't start the combo PHY PLL to calibrate
  phy: spacemit: k1: restore port A state after calibration
  phy: spacemit: k1: program the termination fields properly
  phy: spacemit: k1: set CLKSEL on every lane
  phy: spacemit: k1: don't overwrite whole PLL control registers
  phy: spacemit: k1: power on the combo PHY in USB 3 mode

 drivers/phy/spacemit/phy-k1-pcie.c | 270 +++++++++++++++++++++--------
 1 file changed, 196 insertions(+), 74 deletions(-)


base-commit: a000f2af240eaa996cec92f8d44bad96fdf3f898
-- 
2.55.0