From: SignKirigami <prcups@krgm.moe>
To: qemu-devel@nongnu.org
Cc: Bibo Mao <maobibo@loongson.cn>, SignKirigami <prcups@krgm.moe>
Subject: [PATCH v6 00/26] add LVZ support for TCG
Date: Fri, 13 Nov 2026 16:45:15 +0800 [thread overview]
Message-ID: <cover.1794558695.git.prcups@krgm.moe> (raw)
This patch implements Loongson VirtualiZation (LVZ) extension support
for LoongArch's TCG target. With this patch, it is now possible to start
a nested KVM-accelerated virtual machine on a TCG-emulated virtual machine.
SignKirigami (26):
target/loongarch: add get_sys() helper
target/loongarch: add LVZ feature switcher
target/loongarch: add LVZ CSR metadata
target/loongarch: add vm level 1 definition
target/loongarch: add definition about guest mmu_idx
target/loongarch: move timer initialization to
loongarh_cpu_realizefn()
target/loongarch: add LVZ guest interrupt state
target/loongarch: add LVZ guest timer
target/loongarch: handle return to guest in ertn
target/loongarch: handle LVZ exception and vm_exit
target/loongarch: add host TLBRet and handle
target/loongarch: add gid management functions
target/loongarch: add LVZ parameters to TLB functions
target/loongarch: add LVZ to TLB functions
target/loongarch: add 2-level address mapping to
loongarch_cpu_tlb_fill()
target/loongarch: add LVZ to invtlb 0x0-0x6
target/loongarch: add LVZ to invtlb 0xa-0xe
target/loongarch: add LVZ to ptw
target/loongarch: add LVZ migration state
target/loongarch: add LVZ to CSR operations
target/loongarch: add LVZ to CSR helpers
target/loongarch: add guest CSR operations
target/loongarch: add LVZ CSRs
target/loongarch: translate LVZ guest traps and HVC
target/loongarch: initialize CSR related to LVZ
target/loongarch: exit to vm level 0 for fpd, sxd and asxd of vm level
0
target/loongarch/cpu-csr.h | 38 ++
target/loongarch/cpu-mmu.h | 31 +-
target/loongarch/cpu.c | 117 +++++--
target/loongarch/cpu.h | 90 ++++-
target/loongarch/cpu_helper.c | 52 +--
target/loongarch/csr.c | 102 +++---
target/loongarch/csr.h | 1 +
target/loongarch/disas.c | 9 +
target/loongarch/insns.decode | 7 +
target/loongarch/internals.h | 4 +-
target/loongarch/machine.c | 139 ++++++++
target/loongarch/tcg/csr_helper.c | 131 +++++--
target/loongarch/tcg/helper.h | 37 +-
.../tcg/insn_trans/trans_extra.c.inc | 5 +
.../tcg/insn_trans/trans_privileged.c.inc | 212 ++++++++++--
target/loongarch/tcg/op_helper.c | 37 ++
target/loongarch/tcg/tcg_cpu.c | 89 +++--
target/loongarch/tcg/tlb_helper.c | 324 ++++++++++++------
target/loongarch/tcg/translate.c | 3 +
target/loongarch/translate.h | 1 +
20 files changed, 1107 insertions(+), 322 deletions(-)
base-commit: 49559567804523cb28cad002aa8e97f444e23ad7
--
2.56.0
next reply other threads:[~2026-11-13 8:46 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 8:45 SignKirigami [this message]
2026-11-13 8:45 ` [PATCH v6 01/26] target/loongarch: add get_sys() helper SignKirigami
2026-11-13 8:45 ` [PATCH v6 02/26] target/loongarch: add LVZ feature switcher SignKirigami
2026-11-13 8:45 ` [PATCH v6 03/26] target/loongarch: add LVZ CSR metadata SignKirigami
2026-11-13 8:45 ` [PATCH v6 04/26] target/loongarch: add vm level 1 definition SignKirigami
2026-11-13 8:45 ` [PATCH v6 05/26] target/loongarch: add definition about guest mmu_idx SignKirigami
2026-11-13 8:45 ` [PATCH v6 06/26] target/loongarch: move timer initialization to loongarh_cpu_realizefn() SignKirigami
2026-11-13 8:45 ` [PATCH v6 07/26] target/loongarch: add LVZ guest interrupt state SignKirigami
2026-11-13 8:45 ` [PATCH v6 08/26] target/loongarch: add LVZ guest timer SignKirigami
2026-11-13 8:45 ` [PATCH v6 09/26] target/loongarch: handle return to guest in ertn SignKirigami
2026-11-13 8:45 ` [PATCH v6 10/26] target/loongarch: handle LVZ exception and vm_exit SignKirigami
2026-11-13 8:45 ` [PATCH v6 11/26] target/loongarch: add host TLBRet and handle SignKirigami
2026-11-13 8:45 ` [PATCH v6 12/26] target/loongarch: add gid management functions SignKirigami
2026-11-13 8:45 ` [PATCH v6 13/26] target/loongarch: add LVZ parameters to TLB functions SignKirigami
2026-11-13 8:45 ` [PATCH v6 14/26] target/loongarch: add LVZ " SignKirigami
2026-11-13 8:45 ` [PATCH v6 15/26] target/loongarch: add 2-level address mapping to loongarch_cpu_tlb_fill() SignKirigami
2026-11-13 8:45 ` [PATCH v6 16/26] target/loongarch: add LVZ to invtlb 0x0-0x6 SignKirigami
2026-11-13 8:45 ` [PATCH v6 17/26] target/loongarch: add LVZ to invtlb 0xa-0xe SignKirigami
2026-11-13 8:45 ` [PATCH v6 18/26] target/loongarch: add LVZ to ptw SignKirigami
2026-11-13 8:45 ` [PATCH v6 19/26] target/loongarch: add LVZ migration state SignKirigami
2026-11-13 8:45 ` [PATCH v6 20/26] target/loongarch: add LVZ to CSR operations SignKirigami
2026-11-13 8:45 ` [PATCH v6 21/26] target/loongarch: add LVZ to CSR helpers SignKirigami
2026-11-13 8:45 ` [PATCH v6 22/26] target/loongarch: add guest CSR operations SignKirigami
2026-11-13 8:45 ` [PATCH v6 23/26] target/loongarch: add LVZ CSRs SignKirigami
2026-11-13 8:45 ` [PATCH v6 24/26] target/loongarch: translate LVZ guest traps and HVC SignKirigami
2026-11-13 8:45 ` [PATCH v6 25/26] target/loongarch: initialize CSR related to LVZ SignKirigami
2026-11-13 8:45 ` [PATCH v6 26/26] target/loongarch: exit to vm level 0 for fpd, sxd and asxd of vm level 0 SignKirigami
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