From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 29/37] drm/i915: enable power wells on haswell init Date: Thu, 22 Mar 2012 11:03:22 +0000 Message-ID: References: <1332378612-3814-1-git-send-email-eugeni.dodonov@intel.com> <1332378612-3814-30-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D223A0D8F for ; Thu, 22 Mar 2012 04:03:27 -0700 (PDT) In-Reply-To: <1332378612-3814-30-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Eugeni Dodonov List-Id: intel-gfx@lists.freedesktop.org On Wed, 21 Mar 2012 22:10:04 -0300, Eugeni Dodonov wrote: > This attempts to enable all the available power wells during the > initialization. > > Signed-off-by: Eugeni Dodonov > --- > drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 3b3dc15..2c5b953 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9142,6 +9142,34 @@ static void i915_disable_vga(struct drm_device *dev) > POSTING_READ(vga_reg); > } > > +/* Starting with Haswell, we have different power wells for > + * different parts of the GPU. This attempts to enable them all. > + */ > +static void intel_init_power_wells(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + unsigned long power_wells[] = { > + HSW_PWR_WELL_CTL1, > + HSW_PWR_WELL_CTL2, > + HSW_PWR_WELL_CTL4 > + }; > + int i; > + > + mutex_lock(&dev->struct_mutex); > + > + for (i = 0; i < ARRAY_SIZE(power_wells); i++) { > + int well = I915_READ(power_wells[i]); > + > + if ((well & HSW_PWR_WELL_STATE) == 0) { > + I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); > + if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20)) > + DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); > + } > + } Out of curiosity, can we enable the powerwells in parallel or must it be done sequentially? -Chris -- Chris Wilson, Intel Open Source Technology Centre