From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dhananjay Phadke Date: Tue, 21 Feb 2023 17:14:07 -0800 Subject: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2 In-Reply-To: References: <20230220061745.1973981-1-ryan_chen@aspeedtech.com> <20230220061745.1973981-2-ryan_chen@aspeedtech.com> <2141e513acc750bf26775f5b435f4dccd41244aa.camel@codeconstruct.com.au> Message-ID: List-Id: To: linux-aspeed@lists.ozlabs.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On 2/20/2023 7:32 PM, Ryan Chen wrote: >>>>> +? timeout: >>>>> +??? type: boolean >>>>> +??? description: Enable i2c bus timeout for master/slave (35ms) >>>>> + >>>>> +? byte-mode: >>>>> +??? type: boolean >>>>> +??? description: Force i2c driver use byte mode transmit >>>>> + >>>>> +? buff-mode: >>>>> +??? type: boolean >>>>> +??? description: Force i2c driver use buffer mode transmit >>>> >>>> These three aren't really a property of the hardware, more of the >>>> intended driver configuration. Do they really belong in the DT? >>>> >>> Sorry, I am confused. >>> This is hardware controller mode setting for each i2c transfer. >>> So I add it in property for change different i2c transfer mode. >>> Is my mis-understand the property setting? >> >> It depends what this is configuration is for. >> >> Would you set the transfer mode based on the design of the board? Is there >> something about the physical i2c bus wiring (or some other hardware design >> choice) that would mean you use one setting over another? >> > No, it not depend on board design. It is only for register control for controller transfer behave. > The controller support 3 different trigger mode for transfer. > Byte mode: it means step by step to issue transfer. > Example i2c read, each step will issue interrupt then driver need trigger for next step. > Sr (start read) | D | D | D | P > Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. > The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer. > > Unless these settings like xfer mode are per i2c bus, it could be just a module parameter? Not sure anything other than default mode would be used if DMA mode works for all master/slave transactions. Regards, Dhananjay From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 347C5C636D7 for ; Wed, 22 Feb 2023 01:15:45 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PLyrv3v7Jz3bW2 for ; Wed, 22 Feb 2023 12:15:43 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.a=rsa-sha256 header.s=default header.b=ksjWfUD7; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.microsoft.com (client-ip=13.77.154.182; helo=linux.microsoft.com; envelope-from=dphadke@linux.microsoft.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.a=rsa-sha256 header.s=default header.b=ksjWfUD7; dkim-atps=neutral Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by lists.ozlabs.org (Postfix) with ESMTP id 4PLyqj2LfGz300C; Wed, 22 Feb 2023 12:14:41 +1100 (AEDT) Received: from [192.168.87.25] (unknown [50.35.78.176]) by linux.microsoft.com (Postfix) with ESMTPSA id 33E7320B9C3D; Tue, 21 Feb 2023 17:14:07 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 33E7320B9C3D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1677028447; bh=YTkfcoTrsyGUhPbAsJNW1hFtxJhcxATFUQJzQJ+E840=; h=Date:Subject:To:References:From:In-Reply-To:From; b=ksjWfUD7hL4lluKkN4pyotZAcfERPzfs3CXBvbcHi0Lo+wPjs33I5/pVstNjH2kls q0vfgIXT9nM0kXJiEpsfRXOeOPz9TtJ1UY3OuEK7kN2aV/k9BZrA2waNzRTCKhOztW 1fe+pTK6b/qVT5wvs7gFyCbTFooPdzbctJdO2q/g= Message-ID: Date: Tue, 21 Feb 2023 17:14:07 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2 Content-Language: en-US To: Ryan Chen , Jeremy Kerr , Rob Herring , Krzysztof Kozlowski , Joel Stanley , Andrew Jeffery , Philipp Zabel , "openbmc@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" References: <20230220061745.1973981-1-ryan_chen@aspeedtech.com> <20230220061745.1973981-2-ryan_chen@aspeedtech.com> <2141e513acc750bf26775f5b435f4dccd41244aa.camel@codeconstruct.com.au> From: Dhananjay Phadke In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Sender: "openbmc" On 2/20/2023 7:32 PM, Ryan Chen wrote: >>>>> +  timeout: >>>>> +    type: boolean >>>>> +    description: Enable i2c bus timeout for master/slave (35ms) >>>>> + >>>>> +  byte-mode: >>>>> +    type: boolean >>>>> +    description: Force i2c driver use byte mode transmit >>>>> + >>>>> +  buff-mode: >>>>> +    type: boolean >>>>> +    description: Force i2c driver use buffer mode transmit >>>> >>>> These three aren't really a property of the hardware, more of the >>>> intended driver configuration. Do they really belong in the DT? >>>> >>> Sorry, I am confused. >>> This is hardware controller mode setting for each i2c transfer. >>> So I add it in property for change different i2c transfer mode. >>> Is my mis-understand the property setting? >> >> It depends what this is configuration is for. >> >> Would you set the transfer mode based on the design of the board? Is there >> something about the physical i2c bus wiring (or some other hardware design >> choice) that would mean you use one setting over another? >> > No, it not depend on board design. It is only for register control for controller transfer behave. > The controller support 3 different trigger mode for transfer. > Byte mode: it means step by step to issue transfer. > Example i2c read, each step will issue interrupt then driver need trigger for next step. > Sr (start read) | D | D | D | P > Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. > The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer. > > Unless these settings like xfer mode are per i2c bus, it could be just a module parameter? Not sure anything other than default mode would be used if DMA mode works for all master/slave transactions. Regards, Dhananjay From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E72FC61DA3 for ; Wed, 22 Feb 2023 01:15:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:To:Subject:MIME-Version: Date:Message-ID:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7enc8d9CPXu75X1VjH5c52+mOPccjm8Z3LdrZb771sw=; b=VymKWOgbeEfx9RYOYOGp4fj5hO B83LLUlIcm9b+lXYPibN4IC9OPxoSRkPeehuYLosKmeJWwjNni4VXEnyG0d2EPrZ2HfoT5TlDUrSX n1jInsX1Sh/ftesFDg8xij4jPpAU09nsTqyo86yMfRR6c+BvlFjp0kuW/dMjrOZoVNUFNvGKHRvPM PMmObWWPackMWMa8OvfEJtzxungDz99qAqac7yUnTBB9i1rmHvgpkXZqWtlfxBI/64pWZw768OQPe EMLRLQa+5/PSp6FmMy6fITlPNr1pr9Xc4Gs8cOIsZoEFqr334/EHmbeZonxMTFrNjwux8WnLpyQrf CszckCOg==; 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Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2 Content-Language: en-US To: Ryan Chen , Jeremy Kerr , Rob Herring , Krzysztof Kozlowski , Joel Stanley , Andrew Jeffery , Philipp Zabel , "openbmc@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" References: <20230220061745.1973981-1-ryan_chen@aspeedtech.com> <20230220061745.1973981-2-ryan_chen@aspeedtech.com> <2141e513acc750bf26775f5b435f4dccd41244aa.camel@codeconstruct.com.au> From: Dhananjay Phadke In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230221_171412_172278_C21DC90F X-CRM114-Status: GOOD ( 12.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; 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