From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Jiri Slaby <jirislaby@kernel.org>,
geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com,
sboyd@kernel.org, gregkh@linuxfoundation.org,
p.zabel@pengutronix.de, g.liakhovetski@gmx.de,
lethal@linux-sh.org
Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-serial@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
stable@vger.kernel.org
Subject: Re: [PATCH v2 2/8] serial: sh-sci: Check if TX data was written to device in .tx_empty()
Date: Tue, 12 Nov 2024 10:35:13 +0200 [thread overview]
Message-ID: <d19d12e7-aabb-460c-a37c-6cbd3fe4e459@tuxon.dev> (raw)
In-Reply-To: <3711546e-a551-4cc9-a378-17aab5b426ef@tuxon.dev>
Hi, Jiri,
On 08.11.2024 14:19, Claudiu Beznea wrote:
>>> @@ -885,6 +887,7 @@ static void sci_transmit_chars(struct uart_port *port)
>>> }
>>> sci_serial_out(port, SCxTDR, c);
>>> + s->first_time_tx = true;
>>> port->icount.tx++;
>>> } while (--count > 0);
>>> @@ -1241,6 +1244,8 @@ static void sci_dma_tx_complete(void *arg)
>>> if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
>>> uart_write_wakeup(port);
>>> + s->first_time_tx = true;
>> This is too late IMO. The first in-flight dma won't be accounted in
>> sci_tx_empty(). From DMA submit up to now.
> If it's in-flight we can't determine it's status anyway with one variable.
> We can set this variable later but it wouldn't tell the truth as the TX
> might be in progress anyway or may have been finished?
>
> The hardware might help with this though the TEND bit. According to the HW
> manual, the TEND bit has the following meaning:
>
> 0: Transmission is in the waiting state or in progress.
> 1: Transmission is completed.
>
> But the problem, from my point of view, is that the 0 has double meaning.
>
> I noticed the tx_empty() is called in kernel multiple times before
> declaring TX is empty or not. E.g., uart_suspend_port() call it 3 times,
> uart_wait_until_sent() call it in a while () look with a timeout. There is
> the uart_ioctl() which calls it though uart_get_lsr_info() only one time
> but I presumed the user space might implement the same multiple trials
> approach before declaring it empty.
>
> Because of this I considered it wouldn't be harmful for the scenario you
> described "The first in-flight dma won't be accounted in sci_tx_empty()"
> as the user may try again later to check the status. For this reason I also
> chose to have no extra locking around this variable.
>
> Please let me know if you consider otherwise.
With the above explanation, can you please let me know if you still
consider I should change the approach for this patch?
Thank you,
Claudiu Beznea
next prev parent reply other threads:[~2024-11-12 8:35 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-08 10:05 [PATCH v2 0/8] Add support for the rest of Renesas RZ/G3S serial interfaces Claudiu
2024-11-08 10:05 ` [PATCH v2 1/8] clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs Claudiu
2024-11-08 10:05 ` [PATCH v2 2/8] serial: sh-sci: Check if TX data was written to device in .tx_empty() Claudiu
2024-11-08 10:57 ` Jiri Slaby
2024-11-08 12:19 ` Claudiu Beznea
2024-11-12 8:35 ` Claudiu Beznea [this message]
2024-11-14 6:26 ` Jiri Slaby
2024-11-14 6:29 ` Jiri Slaby
2024-11-14 8:11 ` Claudiu Beznea
2024-11-08 10:05 ` [PATCH v2 3/8] serial: sh-sci: Update the suspend/resume support Claudiu
2024-11-08 10:05 ` [PATCH v2 4/8] arm64: dts: renesas: r9a08g045: Add the remaining SCIF interfaces Claudiu
2024-11-08 10:05 ` [PATCH v2 5/8] arm64: dts: renesas: rzg3s-smarc: Fix the debug serial alias Claudiu
2024-11-08 10:05 ` [PATCH v2 6/8] arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches Claudiu
2024-11-08 10:05 ` [PATCH v2 7/8] arm64: dts: renesas: rzg3s-smarc: Enable SCIF3 Claudiu
2024-11-08 10:05 ` [PATCH v2 8/8] arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1 Claudiu
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