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[95.222.37.56]) by smtp.gmail.com with ESMTPSA id d8-20020a05600c3ac800b00412e84e59d8sm457721wms.44.2024.03.04.03.02.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Mar 2024 03:02:22 -0800 (PST) Message-ID: Date: Mon, 4 Mar 2024 12:02:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RISC-V][tech-server-platform] [RFC 0/2] Add RISC-V Server Platform Reference Board Content-Language: en-US To: "Wu, Fei2" References: <20240304102540.2789225-1-fei2.wu@intel.com> Cc: pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, andrei.warkentin@intel.com, shaolin.xie@alibaba-inc.com, ved@rivosinc.com, sunilvl@ventanamicro.com, haibo1.xu@intel.com, evan.chai@intel.com, yin.wang@intel.com, tech-server-platform@lists.riscv.org, tech-server-soc@lists.riscv.org From: Heinrich Schuchardt In-Reply-To: <20240304102540.2789225-1-fei2.wu@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=185.125.188.122; envelope-from=heinrich.schuchardt@canonical.com; helo=smtp-relay-internal-0.canonical.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.589, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 04.03.24 11:25, Wu, Fei2 wrote: > The RISC-V Server Platform specification[1] defines a standardized set > of hardware and software capabilities, that portable system software, > such as OS and hypervisors can rely on being present in a RISC-V server > platform. This patchset provides a RISC-V Server Platform (RVSP) > reference implementation on qemu which is in compliance with the spec > as faithful as possible. > > The reference board can be running with tag edk2-stable202308 in > upstream edk2 repo[2]. > > The qemu command line used: > > $QEMU -nographic -m 4G -smp 2 \ > -machine rvsp-ref,pflash0=pflash0,pflash1=pflash1 \ > -blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \ > -blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \ > -bios fw_dynamic.bin \ > -drive file=$BRS_IMG,if=ide,format=raw > > Since there is no ACPI table generated in this new machine type, a > corresponding EDK-II platform (WIP) is needed to provide related ACPI > tables. The need for having a platform separate to virt for compliance testing was discussed in RISE in RVI meetings. Thanks for driving this. Will the EDK II platform also generate the SMBIOS table or shall this be handled in QEMU? Will further work in edk2-platforms be needed to provide full compliance with the the server platform specification? Best regards Heinrich > > For testing purposes only, we used a workaround to generate the ACPI > tables in Qemu with a dedicated downstream patch. > > [1] https://github.com/riscv-non-isa/riscv-server-platform > [2] https://github.com/tianocore/edk2.git > > Fei Wu (2): > hw/riscv: Add server platform reference machine > target/riscv: Add server platform reference cpu > > configs/devices/riscv64-softmmu/default.mak | 1 + > hw/riscv/Kconfig | 13 + > hw/riscv/meson.build | 1 + > hw/riscv/server_platform_ref.c | 1248 +++++++++++++++++++ > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 62 + > 6 files changed, 1326 insertions(+) > create mode 100644 hw/riscv/server_platform_ref.c >