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From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	<intel-gfx@lists.freedesktop.org>
Cc: <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH 11/22] drm/i915/vrr: Use trans_vrr_ctl() in intel_vrr_transcoder_disable()
Date: Fri, 24 Oct 2025 19:15:01 +0530	[thread overview]
Message-ID: <d2da7040-4355-4e7b-aa7e-e74085263b4a@intel.com> (raw)
In-Reply-To: <20251020185038.4272-12-ville.syrjala@linux.intel.com>


On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently intel_vrr_disable() writes TRANS_VRR_CTL() with
> trans_vrr_ctl(), whereas intel_vrr_transcoder_disable() always
> writes just a plain 0. Write trans_vrr_ctl() in both places to
> unify the code, allowing for more shared code in the future.
>
> Since the VRR timing generator will be disabled by the
> TRANS_VRR_CTL write it doesn't really matter what we write to
> the register (other than VRR_CTL_VRR_ENABLE that is).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 562a5feadaab..19b38ad77189 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -779,7 +779,8 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
>   	if (!intel_vrr_possible(crtc_state))
>   		return;
>   
> -	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> +		       trans_vrr_ctl(crtc_state));
>   
>   	intel_vrr_wait_for_live_status_clear(display, cpu_transcoder);
>   

  reply	other threads:[~2025-10-24 13:45 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-20 18:50 [PATCH 00/22] drm/i915/vrr: A few fixes and a bunch of cleanup Ville Syrjala
2025-10-20 18:50 ` [PATCH 01/22] drm/i915/vrr: Fix intel_vrr_always_use_vrr_tg()==true on TGL Ville Syrjala
2025-10-24 13:24   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 02/22] drm/i915/lrr: Include SCL in lrr_params_changed() Ville Syrjala
2025-10-24 13:25   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 03/22] drm/i915: Remove the "vblank delay" state dump Ville Syrjala
2025-10-24 13:26   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 04/22] drm/i915/vrr: Compute fixed refresh rate timings the sam way as CMRR timings Ville Syrjala
2025-10-24 13:27   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 05/22] drm/i915/vrr: Reorganize intel_vrr_compute_cmrr_timings() a bit Ville Syrjala
2025-10-24 13:28   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 06/22] drm/i195/vrr: Move crtc_state->vrr.{vmin, vmax} update into intel_vrr_compute_vrr_timings() Ville Syrjala
2025-10-24 13:28   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 07/22] drm/i915/vrr: Move compute_fixed_rr_timings() Ville Syrjala
2025-10-24 13:29   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 08/22] drm/i915/vrr: Extract intel_vrr_set_vrr_timings() Ville Syrjala
2025-10-24 13:30   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 09/22] drm/i915/vrr: Avoid redundant TRANS_PUSH write in intel_vrr_enable() Ville Syrjala
2025-10-24 13:30   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 10/22] drm/i915/vrr: Move EMP_AS_SDP_TL write into intel_vrr_set_transcoder_timings() Ville Syrjala
2025-10-24 13:39   ` Nautiyal, Ankit K
2025-10-24 13:51     ` Ville Syrjälä
2025-10-20 18:50 ` [PATCH 11/22] drm/i915/vrr: Use trans_vrr_ctl() in intel_vrr_transcoder_disable() Ville Syrjala
2025-10-24 13:45   ` Nautiyal, Ankit K [this message]
2025-10-20 18:50 ` [PATCH 12/22] drm/i915/vrr: Extract intel_vrr_tg_disable() Ville Syrjala
2025-10-24 13:45   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 13/22] drm/i915/vrr: Extract intel_vrr_tg_enable() Ville Syrjala
2025-10-24 14:10   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 14/22] drm/i915/vrr: Disable VRR TG in intel_vrr_transcoder_disable() only on always use_vrr_tg() platforms Ville Syrjala
2025-10-24 14:10   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 15/22] drm/i915/vrr: Always write TRANS_VRR_CTL in intel_vrr_set_transcoder_timings() on !always_use_vrr_tg() Ville Syrjala
2025-10-24 14:11   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 16/22] drm/i915/vrr: Remove redundant HAS_VRR() checks Ville Syrjala
2025-10-24 14:12   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 17/22] drm/i915/vrr: Move HAS_VRR() check into intel_vrr_set_transcoder_timings() Ville Syrjala
2025-10-24 14:14   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 18/22] drm/i915/vrr: s/crtc_state/old_crtc_state/ in intel_vrr_transcoder_disable() Ville Syrjala
2025-10-24 14:17   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 19/22] drm/i915/vrr: Nuke intel_vrr_vblank_exit_length() Ville Syrjala
2025-10-24 14:18   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 20/22] drm/i915/vrr: Nuke intel_vrr_vmin_flipline() Ville Syrjala
2025-10-24 14:20   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 21/22] drm/i915/vrr: Update the intel_vrr_extra_vblank_delay() comment Ville Syrjala
2025-10-24 14:21   ` Nautiyal, Ankit K
2025-10-20 18:50 ` [PATCH 22/22] drm/i915/vrr: Check HAS_VRR() first in intel_vrr_is_capable() Ville Syrjala
2025-10-24 14:23   ` Nautiyal, Ankit K
2025-10-21  0:33 ` ✓ i915.CI.BAT: success for drm/i915/vrr: A few fixes and a bunch of cleanup Patchwork
2025-10-21  7:48 ` ✓ CI.KUnit: " Patchwork
2025-10-21  8:21 ` [PATCH 00/22] " Jani Nikula
2025-10-21 10:44 ` ✓ Xe.CI.BAT: success for " Patchwork
2025-10-21 11:40 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-21 15:21 ` ✗ i915.CI.Full: " Patchwork

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